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| order number: 305433, revision: 003us july 2005 intel ? 80333 i/o processor datasheet product features integrated intel xscale ? core ? 500, 667 and 800 mhz ? arm* v5te compliant ? 32 kbyte, 32-way set associative instruction cache with cache locking ? 32 kbyte, 32-way set associative data cache with cache locking. supports write through or write back ? 2 kbyte, 2-way set associative mini- data cache ? 128-entry branch target buffer ? 8-entry write buffer ? 4-entry fill and pend buffer ? performance monitor unit internal bus 333 mhz/64-bit pci express*-to-pci bridges ? x8 pci express* upstream link ? pci express* specification 1.0a compliant ? pci-x bus a (iop bus - atu interface) ? pci-x bus b (slot expansion bus) supports standard pci hot-plug controller ? four output clocks per pci-x bus address translation unit ? 2 kb or 4 kb outbound read queue ? 4 kb outbound write queue ? 4 kb inbound read and write queue ? connects internal bus to pci/x bus a ? messaging unit and expansion rom two programmable 32-bit timers and watchdog timer eight general purpose i/o pins two i 2 c bus interface units dual-ported memory controller ? pc2700 double data rate (ddr333) sdram ? ddrii 400 sdram ? up to 2 gb of 64-bit ddr333 ? up to 1 gb of 64-bit ddrii400 ? optional single-bit error correction, multi-bit detection support (ecc) ? supports unbuffered or registered dimms and discrete sdram ? 32-bit memory support dma controller ? two independent channels connected to internal bus ? two 1kb queues in ch0 and ch1 ? crc-32c calculation application accelerator unit ? raid6 support ? performs optional xor on read data ? compute parity across local memory blocks ? 1 kb/512 byte store queue two uart (16550) units ? 64-byte receive and transmit fifos ? 4-pin, master/slave capable peripheral bus interface ? 8-/16-bit data bus with two chip selects interrupt controller unit ? four priority levels ? vector generation ? sixteen external interrupt pins with high priority interrupt (hpi#) 829-ball, flip chip ball grid array (fcbga) ?37.5 mm 2 and 1.27 mm ball pitch
july 2005 intel ? 80333 i/o processor datasheet datasheet 2 order number: 305433, revision: 003us legal lines and disclaimers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel3 86, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, inte l netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, in tel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved. 80333 datasheet intel ? 80333 i/o processor datasheet july 2005 order number: 305433, revision: 003us 3 contents 1.0 introduction ............................................................................................................................... ..... 7 1.1 about this document ......................................................................................................... .. 7 1.1.1 terminology ............................................................................................................. 7 1.1.2 other relevant documents ..................................................................................... 8 1.2 about the intel ? 80333 i/o processor................................................................................... 9 2.0 features ............................................................................................................................... .........11 2.1 intel xscale ? core..............................................................................................................11 2.2 pci express*-to-pci bridge units ......................................................................................11 2.3 address translation unit .................................................................................................... 12 2.4 memory controller ........................................................................................................... ...12 2.5 application accelerator unit................................................................................................ 12 2.6 peripheral bus interface .................................................................................................... .12 2.7 dma controller .............................................................................................................. .....13 2.8 i 2 c bus interface unit .........................................................................................................13 2.9 messaging unit .............................................................................................................. .....13 2.10 internal bus............................................................................................................... ..........13 2.11 uart units ................................................................................................................. ........13 2.12 interrupt controller unit .................................................................................................. ....14 2.13 gpio ....................................................................................................................... ............14 2.14 smbus unit ................................................................................................................. ........14 3.0 package information ...................................................................................................................15 3.1 functional signal descriptions ...........................................................................................15 3.2 package thermal specifications ........................................................................................55 4.0 electrical specifications .............................................................................................................56 4.1 absolute maximum ratings ................................................................................................56 4.2 v ccpll pin requirements...................................................................................................56 4.3 targeted dc specifications ................................................................................................57 4.4 targeted ac specifications ................................................................................................59 4.4.1 clock signal timings .............................................................................................59 4.4.2 ddr/ddr-ii sdram interface signal timings......................................................61 4.4.3 peripheral bus interface signal timings................................................................63 4.4.4 i 2 c/smbus interface signal timings......................................................................65 4.4.5 uart interface signal timings..............................................................................65 4.4.6 pci express* differential transmitter (tx) output specifications..........................66 4.4.7 pci express* differential receiver (rx) input specifications ................................67 4.4.8 boundary scan test signal timings......................................................................68 4.5 ac timing waveforms ........................................................................................................6 9 4.6 ac test conditions.......................................................................................................... ...73 figures 1 intel ? 80333 i/o processor functional block diagram ...............................................................10 2 829-ball fcbga package diagram............................................................................................37 80333 july 2005 intel ? 80333 i/o processor datasheet datasheet 4 order number: 305433, revision: 003us 3intel ? 80333 i/o processor signal group locations (bottom view) ........................................... 38 4intel ? 80333 i/o processor ballout ? left side (bottom view) ................................................. 39 5intel ? 80333 i/o processor ballout ? right side (bottom view) ............................................... 40 6 clock timing measurement waveforms..................................................................................... 69 7 output timing measurement waveforms ................................................................................... 69 8 input timing measurement waveforms...................................................................................... 70 9i 2 c/smbus interface signal timings .......................................................................................... 70 10 uart transmitter receiver timing............................................................................................ 7 0 11 ddr sdram write timings ...................................................................................................... .71 12 ddr sdram read timings....................................................................................................... 71 13 write preamble/postamble durations........................................................................................ 72 14 ac test load for all signals except pci and ddr sdram ...................................................... 73 15 ac test load for ddr sdram signals ..................................................................................... 73 16 pci/pci-x tov(max) rising edge ac test load ...................................................................... 73 17 pci/pci-x tov(max) falling edge ac test load ..................................................................... 74 18 pci/pci-x tov(min) ac test load ........................................................................................... 74 19 transmitter test load (100 ? differential load) .......................................................................... 74 20 transmitter eye diagram...................................................................................................... ...... 75 21 receiver eye opening (differential) .......................................................................................... .75 tables 1 pin description nomenclature .................................................................................................. .. 15 2 ddr sdram signals ............................................................................................................. .... 16 4 misc sdram signals ............................................................................................................ .... 17 3 ddr-ii sdram signals .......................................................................................................... .... 17 5 peripheral bus interface signals .............................................................................................. .. 18 6 pci express* signals .......................................................................................................... ....... 19 7 b pci (slot expansion) bus signals ........................................................................................... 2 0 8 a pci (iop) bus signals....................................................................................................... ...... 22 10 i 2 c/smbus signals ................................................................................................................ ..... 24 9 interrupt signals ............................................................................................................. ............ 24 11 hot-plug controller signals for parallel 1-slot, no-glue ............................................................. 25 12 uart signals ................................................................................................................. ............ 26 13 test and miscellaneous signals ............................................................................................... .. 28 14 reset strap signals .......................................................................................................... .......... 29 15 power and ground pins ........................................................................................................ ..... 31 16 pin mode behavior ............................................................................................................ ......... 32 17 pin multiplexing for functional modes ........................................................................................ 36 18 fc-style, h-pbga package dimensions.................................................................................... 37 19 829-lead package ? alphabetical ball listings ........................................................................ 41 20 829-lead package ? alphabetical signal listings .................................................................... 48 21 absolute maximum ratings ..................................................................................................... ... 56 22 operating conditions ......................................................................................................... ......... 56 23 dc characteristics........................................................................................................... ........... 57 24 i cc characteristics............................................................................................................... ....... 58 25 pci clock timings ............................................................................................................ .......... 59 26 ddr clock timings ............................................................................................................ ........ 59 27 pci express* clock timings................................................................................................... .... 60 28 ddr sdram signal timings ..................................................................................................... 61 80333 datasheet intel ? 80333 i/o processor datasheet july 2005 order number: 305433, revision: 003us 5 29 ddr-ii sdram signal timings .................................................................................................. 62 30 peripheral bus signal timings................................................................................................ ....63 31 pci signal timings ........................................................................................................... ..........64 32 i 2 c/smbus signal timings ......................................................................................................... 65 33 uart signal timings .......................................................................................................... .......65 34 pci express* tx output specifications ......................................................................................66 35 pci express* rx input specifications......................................................................................... 67 36 boundary scan test signal timings...........................................................................................6 8 37 ac measurement conditions.................................................................................................... ..73 80333 july 2005 intel ? 80333 i/o processor datasheet datasheet 6 order number: 305433, revision: 003us revision history date revision description july 2005 003 updated voltages in section 4.3 may 2005 002 revised: table 16 , modified pin mode behavior for dq[63:32] for 32-bit ddr. table 21 , modified case temperatur e under bias to 95 c max table 22 , modified case temperatur e under bias to 95 c max table 25 , added note 4 march 2005 001 initial release 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 7 1.0 introduction 1.1 about this document this document is the intel ? 80333 i/o processor datasheet . this document contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. detailed functional descriptions other than parametric performance are published in the intel ? 80333 i/o processor developer?s manual . intel corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. intel retains the right to make changes to these specifications at any time, without notice. in particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. in fact, this specification does not imply a commitment by intel to design, manufacture, or sell the product described herein. 1.1.1 terminology to aid the discussion of the intel ? 80333 i/o processor (80333) architecture, the following terminology is used: core processor intel xscale ? core within the 80333 local processor intel xscale ? core within the 80333 host processor processor loca ted upstream from the 80333 local bus 80333 internal bus local memory memory subsystem on the intel xscale ? core ddr sdram or peripheral bus interface busses inbound at or toward the internal bus of the 80333 from the pci interface of the atu outbound at or toward the pci interface of the 80333 atu from the internal bus downstream at or toward a pci express* port directed away from the root complex (to a bus with a higher number) upstream at or toward a pci express* port directed to the pci express* root complex (to a bus with a lower number). qword 64-bit data quantity (8 bytes). dword 32-bit data quantity (4 bytes). word 16-bit data quantity (2 bytes). 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 8 order number: 305433, revision: 002 1.1.2 other relevant documents 1. intel xscale ? core developer?s manual (273473) ? intel corporation 2. pci hot-plug specification, revision 1.1 ? pci special interest group 3. pci express* specification , revision 1.0a ? pci special interest group 4. intel ? 80333 i/o processor developer?s manual (305432) ? intel corporation 5. intel ? 80333 i/o processor design guide (305434) ? intel corporation 6. intel ? 80333 i/o processor specification update (305435) ? intel corporation 7. pci local bus specification , revision 2.3 ? pci special interest group 8. pci-x addendum to the pci local bus specification, revision 1.0a ? pci special interest group 9. pci bus power management interface specification , revision 1.1 ? pci special interest group 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 9 1.2 about the intel ? 80333 i/o processor the 80333 is a multi-function device that integrates the intel xscale ? core (arm* architecture compliant) with intelligent peripherals and pci express*-to-pci bridges. the 80333 consolidates, into a single system: ? intel xscale ? core ? 8 pci express* upstream link ? two pci express*-to-pci bridges supporting pci-x interface on both segments ? pci standard hot-plug controller (segment b) ? address translation unit (pci-to-internal bus application bridge) interfaced to the segment a ? high-performance memory controller ? interrupt controller with up to 16 external interrupt inputs ? two direct memory access (dma) controllers ? application accelerator ? messaging unit ? peripheral bus interface unit ? two i 2 c bus interface units ? two 16550 compatible uarts with flow control (four pins) ? eight general purpose input output (gpio) ports the 80333 is an integrated processor that addresse s the needs of intelligent i/o applications and helps reduce intelligent i/o system costs. pci express* is an industry-standard, high-performance, low-latency system interconnect. the pci express* upstream link of the 80333 is capable of 8 lane widths at 2.5 ghz operation, as defined by the pci express* specification , revision 1.0a. the addition of the intel xscale ? core brings intelligence to the pci express*-to-pci bridges. the 80333 integrates pci express*-to-pci bridges with the atu as an integrated secondary pci device. the upstream pci express* port implements the pci-to-pci bridge programming model according to the pci express* specification , revision 1.0a. the primary address translation unit is compliant with the definitions of an ?application bridge? as found in the pci-x addendum to the pci local bus specification, revision 1.0a. figure 1 on page 10 is a functional block diagram of the 80333. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 10 order number: 305433, revision: 002 figure 1. intel ? 80333 i/o processor functional block diagram !!" # $% & ' ( # ) * #+,- ) ( * #+,- ./ ' * #+,- ) + 0 !#) 1 $ )"1 2 )&& ) 3 45 3 45 # 5 )1 () () 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 11 2.0 features the intel ? 80333 i/o processor combines the intel xscale ? core with powerful new features to create an intelligent i/o processor. this multi-device i/o processor is fully compliant with the pci local bus specification , revision 2.3 and the pci express* specification , revision 1.0a. features specific to the 80333 include the following: the subsections that follow briefly ov erview each feature. refer to the intel ? 80333 i/o processor developer?s manual for full technical descriptions. 2.1 intel xscale ? core the 80333 is based upon the intel xscale ? core. the core processor operates at a maximum frequency of 800 mhz. the instruction cache is 32 kbytes in size and is 32-way set associative. also, the core processor includes a data cache that is 32 kbytes and is 32-way set associative, and a mini data cache that is 2 kbytes and is two-way set associative. 2.2 pci express*-to-pci bridge units the 80333 provides pci express*-to-pci bridge units. these bridge units share a common upstream pci express* interface compliant with the pci express* specification , revision 1.0a. the pci express* interface supports a port lane widt h of eight, for up to 2 gbytes/s per direction (4 gbytes/s total) at 2.5 gbits/s bit rate. the pci-x secondary interfaces support 64-bit 133 mhz, compliant with the pci-x addendum to the pci local bus specification , revision 1.0a. these two secondary pci bus interfaces are referred to as the ?a? and ?b? segment, where the 80333 address translation unit resides on ?a? segment. the ?b? pci bus interface can be used for slot expansion. ? intel xscale ? core ? application accelerator unit ? address translation unit ? memory controller ? peripheral bus interface ? two i2c bus interface unit s ? pci express* 2.5 ghz 8 link ? interrupt controller unit ? messaging unit ? internal bus ? two dma controller s ? two uart units ? eight gpio s ? two pci express*-to-pci bridges to secondary pci-x 133 mhz bus interfaces 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 12 order number: 305433, revision: 002 2.3 address translation unit an address translation unit (atu) allows pci transactions direct access to the 80333 local memory. the atu supports transactions between pci address space and 80333 address space. address translation for the atu is controlled through programmable registers accessible from both the pci interface and the intel xscale ? core. the pci interface of the atu is connected to the 80333 ?a? secondary pci interface of the bridge. up stream access to the pci express* interface is controlled by inverse decode with the address windows of the bridge. dual access to registers allows flexibility in mapping the two addr ess spaces. the atu also supports the power management extended capability configuration header that as defined by the pci bus power management interface specification , revision 1.1. 2.4 memory controller the memory controller allows direct control of a ddr sdram memory subsystem. it features programmable chip selects and support for error correction codes (ecc). the memory controller may be configured for ddr sdram at 333 mhz (with 500 mhz and 667 mhz processors) or ddr-ii sdram at 400 mhz (with 500 mhz and 800 mhz processors). the memory controller is dual-ported, with a dedicated interface for the intel xscale ? core bus interface unit and a second interface to the internal bus. the memory co ntroller supports pipelined access and arbitration control to maximize performance. the memory co ntroller interface configuration support includes unbuffered dimms, registered dimms, and discrete ddr sdram devices. external memory may be configured as host addressable memory or private 80333 memory utilizing the address translation unit and bridges. 2.5 application accelerator unit the application accelerator unit (aa) provides low-latency, high-throughput data transfer capability between the aa unit, the 80333 local memory and the pci bus. it executes data transfers from and to the 80333 local memory, from the pci bus to the 80333 local memory, or from the 80333 local memory to the pci bus. the aa unit performs xor operations, computes parity, generates and verifies an eight byte data integrity field, performs memory block fills, and provides the necessary programming interface. the aa unit in the 80333 has been enhanced to support raid 6 functionality. 2.6 peripheral bus interface the peripheral bus interface unit is a data commu nication path to the flash memory components or other peripherals of an 80333 hardware system. the pbi includes support for either 8/16 bit devices. to perform these tasks at high bandwidth , the bus features a burst transfer capability which allows successive 8/16-bit data transfers. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 13 2.7 dma controller the dma controller allows low-latency, high-throughput data transfers between pci bus agents and the local memory. two separate dma channe ls accommodate data transfers to the pci bus. both channels include a local memory to lo cal memory transfer mode. the dma controller supports chaining and unaligned data transfers. it is programmable through the intel xscale ? core only. 2.8 i 2 c bus interface unit the i 2 c (inter-integrated circuit) bus interface unit allows the intel xscale ? core to serve as a master and slave device residing on the i 2 c bus. the i 2 c unit uses a serial bus developed by philips semiconductor*, consisting of a two-pin interface. the bus allows the 80333 to interface to other i 2 c peripherals and microcontrollers for system ma nagement functions. it requires a minimum of hardware components for an economical system to relay status and reliability information on the i/o subsystem to an external device. also refer to i 2 c peripherals for microcontrollers (philips semiconductor). the 80333 includes two i 2 c bus interface units. 2.9 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 80333. it uses interrupts to notify each system when new data ar rives. the mu has four messaging mechanisms: ? message registers ? doorbell registers ? circular queues ? index registers each messaging mechanism allows a host proces sor or external pci device and the 80333 to communicate through message passing and interrupt generation. 2.10 internal bus the internal bus is a high-speed interconn ect between internal units and intel xscale ? core processor. the internal bus operates at 333 mhz and is 64 bits wide. 2.11 uart units the 80333 includes two uart unit. the uart units allow the intel xscale ? core to serve as a master and slave device residing on the uart bus. the uart units use a serial bus consisting of a four-pin interface. the bus allows the 80333 to in terface to other peripherals and microcontrollers. also refer to 16550 device specification (national semiconductor*). 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 14 order number: 305433, revision: 002 2.12 interrupt controller unit the interrupt controller unit (icu) aggregates inte rrupt sources both external and internal of the 80333 to the intel xscale ? core processor. the icu supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. each source has programmability for masking, core processor interrupt input, and priority. 2.13 gpio the 80333 includes eight general purpose i/o (gpi o) pins which can also be used as external interrupt inputs. 2.14 smbus unit the smbus (system management bus) interface unit allows the 80333 to serve as a slave device on the smbus. smbus is based on the principles of the i 2 c bus and allows the 80333 to interface to system smbus for external access an d control of internal registers. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 15 3.0 package information the 80333 is offered in a flip chip ball grid array (fcbga) package. this is a full grid array package with 829 ball connections. 3.1 functional signal descriptions table 1. pin description nomenclature symbol description c configuration i input pin only o output pin only i/o pin may be either an input or output. od open drain pin pwr power pin gnd ground pin - pin must be connected as described. sync(?) synchronous. signal meets timings relative to a clock. sync(b) synchronous to b_clkin sync(m) synchronous to m_ck[2:0] sync(a) synchronous to a_clkin sync(t) synchronous to tck async asynchronous. inputs may be asynchronous rela tive to all clocks. all asynchronous signals are level-sensitive. rst(r) the pin is reset with pwrgd or rstin# . rst(a) the pin is reset with a_rst# . note that a_rst# is asserted when rstin# or pwrgd is asserted. rst(b) the pin is reset with b_rst# . note that b_rst# is asserted when rstin# or pwrgd is asserted. rst(m) the pin is reset with m_rst# . note that m_rst# is asserted when rstin# or pwrgd is asserted or is asserted with software. rst(t) the pin is reset with trst# . 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 16 order number: 305433, revision: 002 table 2. ddr sdram signals name count type description m_ck[2:0] 3o memory clocks are used to provide the positive differential clocks to the external sdram memory subsystem. m_ck[2:0]# 3o memory clocks are used to provide the negative differential clocks to the external sdram memory subsystem. m_rst# 1 o async memory reset indicates when the memory subsystem has been reset with rstin# or pwrgd or a software reset. ma[13:0] 14 o sync(m), rst(m) memory address bus carries the multiplexed row and column addresses to the sdram memory banks. ba[1:0] 2 o sync(m), rst(m) sdram bank address indicates which of the sdram internal banks are read or written during the current transaction. ras# 1 o sync(m), rst(m) sdram row address strobe indicates the presence of a valid row address on the multiplexed address bus ma[12:0] . cas# 1 o sync(m), rst(m) sdram column address strobe indicates the presence of a valid column address on the multiplexed address bus ma[12:0] . we# 1 o sync(m), rst(m) sdram write enable indicates that the current memory transaction is a write operation. cs[1:0]# 2 o sync(m), rst(m) sdram chip select enables the sdram devices for a memory access (physical banks 0 and 1). cke[1:0] 2 o sync(m), rst(m) sdram clock enable enables the clocks for the sdram memory. deasserting will place the sdram in self-refresh mode. dq[63:0] 64 i/o sync(m), rst(m) sdram data bus carries 64-bit data to and from memory. during a data cycle, read or wr ite data is present on one or more contiguous bytes. during write operations, unused pins are driven to determinate values. cb[7:0] 8 i/o sync(m), rst(m) sdram ecc check bits carry the 8-bit ecc code to and from memory during data cycles. dqs[8:0] 9 i/o sync(m), rst(m) sdram data strobes carry the strobe signals, output in write mode and input in read mode fo r source synchronous data transfer. dm[8:0] 9 o sync(m), rst(m) sdram data mask controls which bytes on the data bus should be written. when dm[8:0] is asserted, the sdram devices do not accept valid data from the byte lanes. to t a l 1 2 0 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 17 table 3. ddr-ii sdram signals name count type description dqs[8:0]# 9 i/o sync(m) rst(m) sdram data strobes carry the differential strobe signals in ddr-ii mode, output in write m ode and input in read mode for source synchronous data transfer. odt[1:0] 2 o sync(m) rst(m) on die termination control, turns on sdram termination during writes. ddrres[2:1] 2i/o compensation for ddr ocd (analog) ddr-ii mode only. to t a l 1 3 table 4. misc sdram signals name count type description ddrcres0 1o analog vss ref pin (analog) both ddrslwcres and ddrimpcres signals connect to this pin through a reference resistor. ddrslwcres 1i/o compensation voltage reference (analog) for ddr driver slew rate control connected through a resistor to ddrcres0 . ddrimpcres 1i/o compensation voltage reference (analog) for ddr driver impedance control connected through a resistor to ddrcres0 . to ta l 3 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 18 order number: 305433, revision: 002 table 5. peripheral bus interface signals name count type description a[22:16] 7 o rst(m) address bus 22:16 carries a demultiplexed version of address bits a22:16. during address ( t a ), wait state ( t w ) and data cycles ( t d ) cycles, a[22:16] represents the upper seven address bits for the current access. a[22:16] allows the pbi interface to address up to 8 mbytes per peripheral device. see ? table 17, ?pin multiplexing for functional modes? on page 36 ? for strap inputs which are muxed onto a[19:16] , and ? ta b le 1 4 , ?reset strap signals? on page 29 ? for a functional description. ad[15:0] 16 i/o rst(m) address/data bus carries 16-bit physical addresses and 8- or 16-bit data to and from memory. during an address ( t a ) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate size ; see below). during a data ( t d ) cycle, bits 0-7, or 0-15 contain read or write data, depending on the corresponding bus width. during write operations to 8-bit wide memory regions, the pbi drives unused bus pi ns high or low. size , which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data trans fers during the bus transaction. ad1 ad0 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfers see ? table 17, ?pin multiplexing for functional modes? on page 36 ? for strap inputs which are muxed onto ad[15:0] , and ? table 14, ?reset strap signals? on page 29 ? for a functional description. a[2:0] 3 o rst(m) address bus 2:0 carries a demultiplexed version of bits 2:0 of the ad[15:0] bus. during an address ( t a ) cycle, bits a[2:0] matches ad[2:0] . during a bursted read data ( t d ) cycle, a[2:0] will represent the current byte address in the bursted transaction. a[2:1] are used for an 16-bit wide peripheral while a[1:0] are used for an 8-bit wide peripheral. see ? table 17, ?pin multiplexing for functional modes? on page 36 ? for strap inputs which are muxed onto a[2:0] , and ? table 14, ?reset strap signals? on page 29 ? for a functional description. ale 1 o rst(m) address latch enable indicates the transfer of a physical address. the pin is asserted during the first address cycle and deasserted during the second address cycle. poe# 1 o rst(m) peripheral output enable indicates whether the bus access is a write or a read with respect to the i/o processor and is valid during the entire bus access. this pin may be used to control the oe# input on peripheral devices. 0 = read 1 = write pwe# 1 o rst(m) peripheral write enable indicates whether the bus access is a write or a read with respect to the i/o processor and is valid during the entire bus access. this pin is use for flash memory accesses and controls the we# input on the rom. 0 = write 1 = read pce[1]# 1 o rst(m) peripheral chip enables specify which of the two memory address ranges are associated with current bus access. the pin remains valid during the entire bus access. pce[0]# 1 o rst(m) peripheral chip enables specify which of the two memory address ranges are associated with current bus access. the pin remains valid during the entire bus access. to t a l 3 1 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 19 table 6. pci express* signals name count type description refclk+ / refclk- 2i pci express* differential clock in: these pins receive a 100 mhz differential clock input from an external source. this clock is used as the reference clock for the pci express* circuitry. pe0tp[7:0] / pe0tn[7:0] 16 o pci express* serial data transmit : these eight differential output pairs carry data and embedded clock for the pci express* port 0 interface. ? 8 mode: all pe0tp[7:0] and pe0tn[7:0] signals are used. ? 4 mode: only pe0tp[3:0] and pe0tn[3:0] signals are used. pe0rp[7:0] / pe0rn[7:0] 16 i pci express* serial data receive : these eight differential input pairs receive data and embedded clock for port 0. ? 8 mode: all pe0rp[7:0] and pe0rn[7:0] signals are used. ? 4 mode: only pe0rp[3:0] and pe0rn[3:0] signals are used. pe_rcompo 1i pci express rcomp : connected to external reference resistor. output current path, used to compensate pci express* driver and rx termination. pe_icompi 1i pci express rcomp in: connected to the same external resistor as pe_rcompo on the board, for input voltage sensing comparator. to ta l 3 6 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 20 order number: 305433, revision: 002 table 7. b pci (slot expansion) bus signals (sheet 1 of 2) name count type description b_ad[31:0] 32 i/o sync(b) rst(b) b pci address/data is the multiplexed pci address and lower 32 bits of the data bus. b_ad[63:32] 32 i/o sync(b) rst(b) b pci address/data is the upper 32 bits of the pci data bus driven during the data phase. b_par 1 i/o sync(b) rst(b) b pci bus parity is even parity across b_ad[31:0] and b_c/be[3:0]# . b_par64 1 i/o sync(b) rst(b) b pci bus upper dword parity is even parity across b_ad[63:32] and b_c/be[7:4]# . b_c/be[7:0]# 8 i/o sync(b) rst(b) b pci bus command and byte enables are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, t hey are used as byte enables for b_ad[63:0] . b_gnt[4]# 1 o sync(b) rst(b) b secondary pci bus grant signals sent to device 4 on the b- segment pci bus. b_gnt[3]# 1 o sync(b) rst(b) b secondary pci bus grant signals sent to device 3 on the b- segment pci bus. b_gnt[2]# 1 o sync(b) rst(b) b secondary pci bus grant signal sent to device 2 on the b- segment pci bus. b_gnt[1]# 1 o sync(b) rst(b) b secondary pci bus grant signal sent to device 1 on the b- segment pci bus. b_gnt[0]# 1 o sync(b) rst(b) b pci bus grant is the grant signal sent to device 0 on the b- segment pci bus. b_req64# 1 i/o sync(b) rst(b) b pci bus request 64-bit transfer indicates the attempt of a 64- bit transaction on the pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of b_ack64# . b_req[4]# 1 i sync(b) b pci bus requests is the request signal for device 4 on the b- segment pci bus. b_req[3]# 1 i sync(b) b pci bus requests is the request signal for device 3 on the b- segment pci bus. b_req[2]# / b_hm66en 1 i sync(b) b pci bus requests is the request signal for device 2 on the b- segment pci bus. pci 66 enable is used to determine when the slot is pci 66 mhz capable. this signal is only valid for hot-plug 1-slot mode. b_req[1]# 1 i sync(b) b pci bus requests is the request signal for device 1 on the b-segment pci bus. b_req[0]# 1 i sync(b) b pci bus requests are the request signals from device 0 on the b-segment secondary pci bus. b_ack64# 1 i/o sync(b) rst(b) b pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. b_frame# 1 i/o sync(b) rst(b) b pci bus cycle frame is asserted to indicate the beginning and duration of an access. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 21 b_irdy# 1 i/o sync(b) rst(b) b pci bus initiator ready indicates the initiating agent?s ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the address/data bus. during a read, it indicates the processor is ready to accept the data. b_trdy# 1 i/o sync(b) rst(b) b pci bus target ready indicates the target agent?s ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the address/data bus. during a write, it indicates the target is ready to accept the data. b_stop# 1 i/o sync(b) rst(b) b pci bus stop indicates a request to stop the current transaction on the pci bus. b_devsel# 1 i/o sync(b) rst(b) b pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. b_lock# 1 i/o sync(b) rst(b) b pci bus lock indicates whether or not a transaction is establishing a lock across the bridge. b_serr# 1 i/o od sync(b) rst(b) b pci bus system error is driven for address parity errors on the pci bus. b_perr# 1 i/o sync(b) rst(b) b pci bus parity error is asserted when a data parity error occurs during a pci bus transaction. b_m66en 1i/o b pci bus 66 mhz enable indicates the speed of the pci bus. when this signal is sampled high the pci bus speed is 66 mhz, when low, the bus speed is 33 mhz. b_pme# 1 i sync(b) power management event signal is used to request a change in the device or system power state. b_pcixcap 1i b pci-x capability analog pad that selects pci/x mode and frequency capabilities. non-standar d, special purpose analog pin. b_clko[4:0] 5o b pci bus output clocks are used to drive external logic on the secondary pci bus. b_clkout 1o b pci bus output clock is used to drive b_clkin when secondary bus clocks are enabled. b_clkin 1i b pci bus input clock provides the timing for all pci transactions. typically connected on the board to b_clkout . provides timing clock for all b-segment pci interfaces. b_rst# 1o b pci bus reset is an output based on rstin# or pwrgd . it brings pci-specific register s, sequencers, and signals to a consistent state. when rstin# is asserted or pwrgd is deasserted, or the secondary bridge re set bit is asserted, it causes b_rst# to assert and: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as b_serr# are floated b_rst# may be asynchronous to b_clkin when asserted or deasserted. although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. b_rcomp 1i/o pci resistor compensation pin is an analog pad that connects to a board resistor to control all b segment pci output driver strengths (analog). total 106 table 7. b pci (slot expansion) bus signals (sheet 2 of 2) name count type description 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 22 order number: 305433, revision: 002 table 8. a pci (iop) bus signals (sheet 1 of 2) name count type description a_ad[31:0] 32 i/o sync(a) rst(a) a pci address/data is the multiplexed pci address and lower 32 bits of the data bus. a_ad[63:32] 32 i/o sync(a) rst(a) a pci address/data is the upper 32 bits of the pci data bus. a_par 1 i/o sync(a) rst(a) a pci bus parity is even parity across a_ad[31:0] and a_c/be[3:0]# . a_par64 1 i/o sync(a) rst(a) a pci bus upper dword parity is even parity across a_ad[63:32] and a_c/be[7:4]# . a_c/be[3:0]# 4 i/o sync(a) rst(a) a pci bus command and byte enables are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as the byte enables for a_ad[31:0] . a_c/be[7:4]# 4 i/o sync(a) rst(a) a pci byte enables are used as byte enables for a_ad[63:32] during secondary pci data phases. a_req64# 1 i/o sync(a) rst(a) a pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the secondar y pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of a_ack64# . a_ack64# 1 i/o sync(a) rst(a) a pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. a_frame# 1 i/o sync(a) rst(a) a pci bus cycle frame is asserted to indicate the beginning and duration of an access. a_irdy# 1 i/o sync(a) rst(a) a pci bus initiator ready indicates the initiating agent?s ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the secondary address/data bus. during a read, it indicates the processor is ready to accept the data. a_trdy# 1 i/o sync(a) rst(a) a pci bus target ready indicates the target agent?s ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the secondary address/data bus. during a write, it indicates the target is ready to accept the data. a_stop# 1 i/o sync(a) rst(a) a pci bus stop indicates a request to stop the current transaction on the secondary pci bus. a_devsel# 1 i/o sync(a) rst(a) a pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. a_serr# 1 i/o od sync(a) rst(a) a pci bus system error is driven for address parity errors on the secondary pci bus. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 23 a_rst# 1 o async a pci bus reset is an output based on rstin# or pwrgd . it brings pci-specific registers, sequencers, and signals to a consistent state. when rstin# is asserted or pwrgd is deasserted, or the secondary bridge reset bit is asserted, it causes a_rst# to assert and: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as a_serr# are floated. a_rst# may be asynchronous to a_clkin when asserted or deasserted. although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. a_perr# 1 i/o sync(a) rst(a) a pci bus parity error is asserted when a data parity error during a secondary pci bus transaction. a_lock# 1 i/o sync(a) rst(a) a pci bus lock indicates the need to perform an atomic operation on the secondary pci bus. a_clko[3:0] 4o a pci bus output clocks are used to drive ex ternal logic on the secondary pci bus. a_clkout 1o a pci bus output clock is used to drive a_clkin when the io processor provides secondary bus clocks. a_clkin 1i a pci bus input clock provides the timing for all pci transactions. typically connected on the board to a_clkout . provides the timing clock for all a segment pci interfaces. a_m66en 1i/o a pci bus 66 mhz enable indicates the speed of the secondary pci bus. when this signal is high, the bus speed is 66 mhz and when it is low, the bus speed is 33 mhz. a_pme# 1 i sync(a) power management event signal is used to request a change in the device or system power state. a_req[3:0]# 4 i sync(a) a pci bus requests are the request signals from devices 3 through 0 on the a pci bus. a_gnt[3:0]# 4 o sync(a) rst(a) a pci bus grant are grant signals sent to devices 3 through 0 on the a pci bus. a_pcixcap 1i a pci-x capability is an analog pad that selects pci/x mode and frequency capabilities. non-standard, special purpose analog pin. a_rcomp 1i/o pci resistor compensation pin is an analog pad that connects to the board resistor to control all a segment pci output driver strengths (analog). total 103 table 8. a pci (iop) bus signals (sheet 2 of 2) name count type description 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 24 order number: 305433, revision: 002 table 9. interrupt signals name count type description xint[7:0]# 8 i async interrupt inputs: xint[7:0]# interrupts are directed to the input of the ioapic, or the interrupt controller inputs. when directed to the interrupt controller inputs, then the inputs can be steered to either the fiq or irq internal interrupt input of the core. by default, xint[7:4]# interrupts are directed to the input of the b ioapic and xint[3:0]# interrupts are directed to the input of the aioapic. these interrupt pins are level sensitive. hpi# 1 i async high priority interrupt causes a high priority interrupt to the i/o processor. this pin is leve l-detect only and is internally synchronized. to t a l 9 table 10. i 2 c/smbus signals name count type description scl0 1i/oi 2 c clock provides synchronous operation of the i 2 c bus zero. scd0 1i/oi 2 c data is used for data transfer and arbitration of the i 2 c bus zero. scl1/sclk 1i/o i 2 c clock provides synchronous operation of the i 2 c bus zero. sm bus clock provides synchronous operation of the sm bus. scd1/sdta 1i/o i 2 c data is used for data transfer and arbitration of the i 2 c bus zero. sm bus data is used for data transfer and arbitration of the sm bus. to t a l 4 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 25 table 11. hot-plug controller signa ls for parallel 1-slot, no-glue name count type description b_hpwrflt# 1 i sync(b) rst(b) parallel mode hot-plug power controller fault indication for over- current/under-volt status. when asserted, the device (when enabled) may assert a slot reset and disconnects the slot from the bus. b_hmrl# 1 i sync(b) rst(b) parallel mode hot-plug status of the slot 1 mrl sensor switch, when asserted it indicates the mrl latch is closed. when a platform does not support mrl sensors, this must be wired to a logic low level. b_hprsnt2# 1 i sync(b) parallel mode hot-plug prsnt2 signal is used to indicate whether a card is installed in the slot and its power requirements. these signals are directly connected to the present bits on the pci card. b_hpwren 1 o sync(b) rst(b) parallel mode hot-plug power enable signal connected to on- board slot specific power controller to regulate current and voltage of the slot. b_hprsnt1# 1 i sync(b) rst(b) parallel mode hot-plug prsnt1 signal is used to indicate whether a card is installed in the slot and its power requirements. these signals are directly connected to the present bits on the pci card. b_hatnled# 1 o sync(b) rst(b) parallel mode hot-plug attention indicator led signal that is yellow or amber in color. b_hpwrled# 1 o sync(b) rst(b) parallel mode hot-plug power indicator led signal that is green in color. b_hbutton# 1 i sync(b) rst(b) parallel mode hot-plug attention button input from the slot. when low, this indicates that the operat or has requested attention. when an attention button is not implemented, this input must be wired to a logic high level. b_hreset# 1o parallel mode reset output signal . this output signal is always ?on?, therefore, it does not tri-state during boundary scan. to ta l 9 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 26 order number: 305433, revision: 002 table 12. uart signals (sheet 1 of 2) name count type description gpio[0] / u0_rxd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. serial input : serial data input from device pin to receive shift register. gpio[1] / u0_txd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. serial output : composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. gpio[2] / u0_cts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. clear to send : when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart should stop transmission to prevent overflow of the receiving uarts buffer. the cts# signal is a modem- status input whose condition may be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode : when not in autoflow mode, bit 4 (cts) of the modem status register (msr) indicates the state of cts# . bit 4 is the complement of the cts# signal. bit 0 (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user may program the uart to interrupt the processor when dcts changes state. the programmer may then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user may not receive an msr interrupt when cts# reasserts. this occurs because disabling the uart also disables interrupts. as a wo rkaround, the user may use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode : note: in autoflow mode, the uart transmit circuitry will check the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. gpio[3] / u0_rts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. request to send : when low, this informs the remote device that the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode : the rts# output signal may be asserted by setting bit 1 (rts) of the modem control register to a 1. the rts bit is the complement of the rts# signal. autoflow mode : rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 27 gpio[4] / u1_rxd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. serial input : serial data input from device pin to receive shift register. gpio[5] / u1_txd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. serial output : composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. gpio[6] / u1_cts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. clear to send : when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart should stop transmission to prevent overflow of the receiving uarts buffer. the cts# signal is a modem- status input whose condition may be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode : when not in autoflow mode, bit 4 (cts) of the modem status register (msr) indicates the state of cts# . bit 4 is the complement of the cts# signal. bit 0 (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user may program the uart to interrupt the processor when dcts changes state. the programmer may then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user may not receive an msr interrupt when cts# reasserts. this occurs becaus e disabling the uart also disables interrupts. as a workaround, the user may use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode: note: in autoflow mode, the uart transmit circuitry will check the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. gpio[7] / u1_rts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. request to send : when low, this informs the remote device that the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode : the rts# output signal may be asserted by setting bit 1 (rts) of the modem control register to a 1. the rts bit is the complement of the rts# signal. autoflow mode : rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programm ed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. to ta l 8 table 12. uart signals (sheet 2 of 2) name count type description 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 28 order number: 305433, revision: 002 table 13. test and miscellaneous signals name count type description tck 1i test clock provides clock input for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the device on the rising clock edge and data is clocked out on the falling clock edge. tdi 1 i sync(t) test data input is the jtag serial input pin. tdi is sampled on the rising edge of tck , during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. tdo 1 o sync(t) rst(t) test data output is the serial output pin for the jtag feature. tdo is driven on the falling edge of tck during the shift-ir and shift- dr states of the test access port. at other times, tdo floats. the behavior of tdo is independent of rstin# or pwrgd . trst# 1 i async test reset asynchronously resets the test access port controller function of ieee 1149 boundary scan testing (jtag). this pin has a weak internal pull-up. tms 1 i sync(t) test mode select is sampled on the rising edge of tck to select the operation of the test logic for ieee 1149 boundary scan testing. this pin has a weak internal pull-up. n/c 7- no connect . do not connect to any signal, power or ground. pwrdelay 1 i async power fail delay is used to delay the reset of the memory controller in a power-fail condition. this allows the self-refresh command to be sent to the ddr sdram array. pwrgd 1 i async power supply good : signal that specifies that the motherboard power supply has stabilized. this signal is used to asynchronously reset the 80333 when it is low. the low period of this signal must be long enough for the system power supply to stabilize and for the base plls to lock. note: this is the same signal as perst# which is described in the pci express* card electromechanical specification , revision 1.0a. rstin# 1 i async reset input brings pci-specific registers, sequencers, and signals to a consistent state. when rstin# is asserted: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as b_serr# are floated. rstin# may be asynchronous to b_clkin when asserted or deasserted. although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. to t a l 1 5 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 29 table 14. reset strap signals (sheet 1 of 2) name count type description retry 1c configuration retry mode : retry is latched on the rising (asserting) edge of pwrgd and determines when the pci interface of the atu will disable pci configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the pci configuration and status register. 0 = configuration cycles enabled (requires pull down resistor.) 1 = configuration retry enabled in the atu (default mode) note: muxed onto signal ad[6] , see table 17, ?pin multiplexing for functional modes? on page 36 . core_rst# 1c core reset mode is latched on the rising (asserting) edge of pwrgd and determines when the intel xscale ? core is held in reset until the processor reset bit is cleared in pci configuration and status register. 0 = hold in reset. (requires pull-down resistor.) 1 = do not hold in reset. (default mode) note: muxed onto signal ad[5] , see table 17, ?pin multiplexing for functional modes? on page 36 . p_boot16# 1c bus width is latched on the rising (asserting) edge of pwrgd, it sets the default bus width for the pbi memory boot window. 0 = 16 bits wide (requires a pull-down resistor.) 1 = 8 bits wide (default mode) note: muxed onto signal ad[4] , see table 17, ?pin multiplexing for functional modes? on page 36 . mem_type 1c memory type : mem_type is latched on the rising (asserting) edge of pwrgd and it defines the speed of the ddr sdram interface. 0 = ddr-ii sdram at 400 mhz (required pull-down resistor.) 1 = ddr sdram at 333 mhz (default mode) note: muxed onto signal ad[2] , see table 17, ?pin multiplexing for functional modes? on page 36 . a_pcix133en 1c pci bus segment ?a? 133 mhz enable: a_pcix133en is latched on the rising (asserting) edge of pwrgd and it determines the maximum pci-x mode operating frequency. 0 = 100 mhz enabled (requires pull down resistor). 1 = 133 mhz enabled (default mode). note: muxed onto signal ad[3] , see table 17, ?pin multiplexing for functional modes? on page 36 . b_pcix133en 1c pci bus segment ?b? 133 mhz enable : b_pcix133en latched on rising (asserting) edge of pwrgd and determines maximum pci-x mode operating frequency. 0 = 100 mhz enabled (requires pull down resistor.) 1 = 133 mhz enabled (default mode) note: muxed onto signal ad[10] , see table 17, ?pin multiplexing for functional modes? on page 36 . 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 30 order number: 305433, revision: 002 b_hslot[3:0] 4c number of slots : b_hslot[3:0] latched on rising (asserting) edge of pwrgd and indicates when the ?b? pci-x bus interface standard hot-plug controller is enabled, the total number of slots in both hot-plug enabled mode and disabled mode, and the hot- plug mode. b_hslot[3] enables hot-plug when high and disables hot-plug when low. hot-plug disabled hot-plug enabled 0000 = 1 slot 1000 = reserved 0001 = 2 slots 1001 = reserved 0010 = 3 slots 1010 = reserved 0011 = 4 slots 1011 = reserved 0100 = 5 slots 1100 = reserved 0101 = 6 slots 1101 = reserved 0110 = 7 slots 1110 = reserved 0111 = 8 slots 1111 = parallel 1-slot-no-glue note: 1111 is default m ode. note: muxed onto signal ad[15:12] , see table 17, ?pin multiplexing for functional modes? on page 36 . smb_ma5 smb_ma3 smb_ma2 smb_ma1 4c manageability address (ma) : latched on rising (asserting) edge of pwrgd and maps to ma bit 5, 3, 2, and 1, where ma bits[7:0] represent the address the smbus slave port will respond to when access is attempted. 0 = (requires pull down resistor.) 1 = (default mode) note: muxed onto signal a[19:16] , see table 17, ?pin multiplexing for functional modes? on page 36 . pciodt_en 1c pci bus odt enable : pciodt_en is latched on the rising (asserting) edge of pwrgd , and determines when the pci-x interface will have on-die termination enabled. pciodt_en is valid for both a and b segments. the following signals are affected by pciodt_en : a_ack64# , a_ad[63:32] , a_c/be[7:4]# , a_devsel# , a_frame# , a_irdy# , a_lock# , a_m66en , a_par64 , a_perr# , a_req[3:0]# , a_req64# , a_serr# , a_stop# , a_trdy# , b_ack64# , b_ad[63:32] , b_c/be[7:4]# , b_devsel# , b_frame# , b_irdy# , b_lock# , b_m66en , b_par64 , b_perr# , b_req[4:0]# , b_req64# , b_serr# , b_stop# , b_trdy# , xint[7:0]# 0 = odt disabled (requires pull-down resistor). 1 = odt enabled (default mode). note: muxed onto signal a[20] , see table 17, ?pin multiplexing for functional modes? on page 36 . pd1 1c pull-down resistor is required for default mode. note: muxed onto signal ad[7] , see table 17, ?pin multiplexing for functional modes? on page 36 . to ta l 1 6 table 14. reset strap signals (sheet 2 of 2) name count type description 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 31 table 15. power and ground pins name count type description v ccpll[1-5] 5pwr pll 1-5 power is a separate v cc15 supply ball for the phase lock loop clock generator. it is to be connected to the board v cc15 plane. each v ccpll requires a low-pass filter circuit to reduce noise- induced clock jitter and its effects on timing relationships. see the intel ? 80333 i/o processor design guide for more information. v cc33 49 pwr 3.3 v power balls to be connected to a 3.3 v power board plane. v cc25/18 29 pwr 2.5 v/1.8 v power balls to be connected to a 2.5 v or 1.8 v power board plane, dependent on ddr or ddrii mode. v cc15 56 pwr 1.5 v power balls to be connected to a 1.5 v power board plane. vcc15 = core vcc15e = pci express* v cc13 7pwr 1.3 v power balls to be connected to a 1.35 v power board plane. pe_vccbg 1pwr pci express* band gap analog ref power : 2.5 v power for analog reference circuit, separated from all other vcc signals. requires a low-pass filter. ddr_vref 1pwr sdram voltage reference is used to supply the reference voltage to the differential inputs of the memory controller pins. v ss 218 gnd ground balls to be connected to a ground board plane. v ss a[1-5] 5gnd analog ground balls need to be connected to the appropriate v ccpll filter, and not to board ground. pe_vssbg 1gnd pci express* band gap analog ground: ground for analog reference circuit, separated from all other vss signals. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 32 order number: 305433, revision: 002 table 16. pin mode behavior (sheet 1 of 4) pin reset norm ecc off 32-bit ddr 32-bit b_pci 32-bit a_pci m_ck[2:0] x 1 vo vo vo - - m_ck[2:0]# x 1 vo vo vo - - m_rst# 0 vovovo - - ma[13:0] 0 ? vo vo vo - - ba[1:0] 0 ? vo vo vo - - ras# 1 ? vo vo vo - - cas# 1 ? vo vo vo - - we# 1 ? vo vo vo - - cs[1:0]# 1 ? vo vo vo - - cke[1:0] 0 ? vo vo vo - - dq[63:32] z ? vb vb id,z - - dq[31:0] z ? vb vb vb - - cb[7:0] z ? vb vb vb - - dqs[8] z ? vb id,z vb - - dqs[7:4] z ? vb vb id,z - - dqs[3:0] z ? vb vb vb - - dqs[8]# z ? vb id,z vb - - dqs[7:4]# z ? vb vb id,z - - dqs[3:0]# z ? vb vb vb - - dm[8] z ? vo z vo - - dm[7:4] z ? vo vo z - - dm[3:0] z ? vo vo vo - - ddr_vref vi vi vi vi - - odt[1:0] 2 0 vovovo - - ddrres[2:1] z ? vb vb vb - - ddrcres0 vo vo vo vo - - ddrslwcres vb vb vb vb - - ddrimpcres vb vb vb vb - - a[22:16] hvo---- ad[15:0] hvb---- a[2:0] hvo---- ale 0vo---- notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled h = pulled up to v cc pd = pull-up disabled ao = analog output level l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin vo = a valid output level is driven vi = need to drive a valid input level ? = after power fail sequence completes ? = caused by hi-z from mode pins only 1. clocks become valid right before m_rst# deasserts. 2. odt signal to be low during power up and initialization per ddr-ii jedec specification. 3. high impedance common mode dc voltage driven per pci express* specification , revision 1.0. 4. input disabled, but termination on, per pci express* specification , revision 1.0. 5. hot-plug controller signals are pulled up when shpc is disabled (b_hslot[3] = 0 on rising edge of pwrgd.) 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 33 poe# 1vo---- pwe# 1vo---- pce[1]# hvo---- pce[0]# hvo---- refclk+ refclk- vivi---- pe0tp[7:0] pe0tn[7:0] z 3 vo---- pe0rp[7:0] pe0rn[7:0] id 4 vi---- pe_rcompo vi vi pe_icompi vi vi b_ad[63:32] 0vb - - h - b_ad[31:0] 0vb - - vb - b_par 0vb - - vb - b_par64 zvb - - h - b_c/be[7:4]# 0vb - - h - b_c/be[3:0]# 0vb - - vb b_gnt[4:0]# hvo---- b_req64# vovb---- b_req[4:0]# vivi---- b_ack64# zvb---- b_frame# zvb---- b_irdy# zvb---- b_trdy# vovb---- b_stop# vovb---- b_devsel# vovb---- b_lock# zvb---- b_serr# zvb---- b_clkin vivi---- pwrgd vivi---- rstin# vivi---- b_rst# vovo---- table 16. pin mode behavior (sheet 2 of 4) pin reset norm ecc off 32-bit ddr 32-bit b_pci 32-bit a_pci notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled h = pulled up to v cc pd = pull-up disabled ao = analog output level l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin vo = a valid output level is driven vi = need to drive a valid input level ? = after power fail sequence completes ? = caused by hi-z from mode pins only 1. clocks become valid right before m_rst# deasserts. 2. odt signal to be low during power up and initialization per ddr-ii jedec specification. 3. high impedance common mode dc voltage driven per pci express* specification , revision 1.0. 4. input disabled, but termination on, per pci express* specification , revision 1.0. 5. hot-plug controller signals are pulled up when shpc is disabled (b_hslot[3] = 0 on rising edge of pwrgd.) 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 34 order number: 305433, revision: 002 b_perr# zvb---- b_m66en vbvb---- b_pme #vivi b_pcixcap vivi---- b_clko[4:0] vovo---- b_clkout vovo---- a_ad[63:32] zvb---h a_ad[31:0] 0vb---- a_par 0vb---- a_par64 zvb---h a_c/be[3:0]# 0vb---- a_c/be[7:4]# zvb---h a_req64# vovb---- a_ack64# zvb---- a_frame# zvb---- a_irdy# zvb---- a_trdy# vovb---- a_stop# vovb---- a_devsel# vovb---- a_serr# zvb---- a_rst# vovo---- a_perr# zvb---- a_lock# zvb---- a_clko[3:0] vovo---- a_clkout vovo---- a_clkin vivi---- a_m66en vbvb---- a_pme# vi vi a_req[3:0]# vivi---- a_gnt[3:0]# hvo---- a_pcixcap vivi---- a_rcomp aoao---- table 16. pin mode behavior (sheet 3 of 4) pin reset norm ecc off 32-bit ddr 32-bit b_pci 32-bit a_pci notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled h = pulled up to v cc pd = pull-up disabled ao = analog output level l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin vo = a valid output level is driven vi = need to drive a valid input level ? = after power fail sequence completes ? = caused by hi-z from mode pins only 1. clocks become valid right before m_rst# deasserts. 2. odt signal to be low during power up and initialization per ddr-ii jedec specification. 3. high impedance common mode dc voltage driven per pci express* specification , revision 1.0. 4. input disabled, but termination on, per pci express* specification , revision 1.0. 5. hot-plug controller signals are pulled up when shpc is disabled (b_hslot[3] = 0 on rising edge of pwrgd.) 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 35 b_rcomp aoao---- xint[7:4]# vivi---- xint[3:0]# vivi---- hpi# vivi---- b_hpwrflt# (5) vivi---- b_hmrl# (5) vivi---- b_hprsnt2# (5) vivi---- b_hpwren (5) zvo---- b_hprsnt1# (5) vivi---- b_hatnled# (5) zvo---- b_hpwrled# (5) zvo---- b_hbutton# (5) vivi---- scl0 , scd0 , scl1 / sclk , scd1 / sdta hvb---- gpio[3:0] / u0_rts# , u0_cts# , u0_txd , u0_rxd , vivb---- gpio[7:4] / u1_rts# , u1_cts# , u1_txd , u1_rxd vivb---- tck vivi---- tdi hh---- tdo vo ? vo---- trst# hh---- tms hh---- pwrdelay vivi---- pwrgd vivi---- nc[3:0] hh---- table 16. pin mode behavior (sheet 4 of 4) pin reset norm ecc off 32-bit ddr 32-bit b_pci 32-bit a_pci notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled h = pulled up to v cc pd = pull-up disabled ao = analog output level l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin vo = a valid output level is driven vi = need to drive a valid input level ? = after power fail sequence completes ? = caused by hi-z from mode pins only 1. clocks become valid right before m_rst# deasserts. 2. odt signal to be low during power up and initialization per ddr-ii jedec specification. 3. high impedance common mode dc voltage driven per pci express* specification , revision 1.0. 4. input disabled, but termination on, per pci express* specification , revision 1.0. 5. hot-plug controller signals are pulled up when shpc is disabled (b_hslot[3] = 0 on rising edge of pwrgd.) 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 36 order number: 305433, revision: 002 table 17. pin multiplexing for functional modes pin reset straps a[20] pciodt_en ad[15] b_hslot[3] ad[14] b_hslot[2] ad[13] b_hslot[1] ad[12] b_hslot[0] ad[10] b_pcix133en ad[7] pd1 ad[6] retry ad[5] core_rst# ad[4] p_boot16# ad[3] a_pcix133en ad[2] mem_type a[19] smb_ma5 a[18] smb_ma3 a[17] smb_ma2 a[16] smb_ma1 scl1 / sclk - scd1 / sdta - gpio[0] / u0_rxd - gpio[1] / u0_txd - gpio[2] / u0_cts# - gpio[3] / u0_rts# - gpio[4] / u1_rxd - gpio[5] / u1_txd - gpio[6] / u1_cts# - gpio[7] / u1_rts# - 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 37 figure 2. 829-ball fcbga package diagram table 18. fc-style, h-pbga package dimensions 829-pin bga symbol minimum maximum a 2.392 2.942 a1 0.50 0.70 a3 0.742 0.872 b 0.61 ref. c 1.15 1.37 d 37.45 37.55 e 37.45 37.55 f1 9.88 ref. f2 10.16 ref. e 1.27 ref. s1 0.97 ref. s2 0.97 ref. measurement in millimeters. b1230-02 e d f1 f2 die laser mark s2 s1 pin #1 corner ?b e a3 a a1 c top view bottom view side view seating plane a 1234 b c d e f g h j k l n p r t u v w y aa ab ac ad ae af ag ah aj m 5 6 7 8 9 10111213141516171819 202122232425 26272829 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 38 order number: 305433, revision: 002 figure 3. intel ? 80333 i/o processor signal group locations (bottom view) b1215-01 ddr / ddrii sdram shpc gpio pbi vcc/vss pci-x bus b pci-x bus a pci express aj a h a g a f a e a d a c a b a a y w v u t r p n m l k j h g f e d c b a aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1234567891011121314151617181920 21 22 23 24 25 26 27 28 29 1234567891011121314151617181920 21 22 23 24 25 26 27 28 29 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 39 figure 4. intel ? 80333 i/o processor ballout ? left side (bottom view) ! " ! #$ " ! " ! " ! " ! " ! ! % # & #$ " $ " ! " ! " ! " ! " ! " ! " ! " ! " ! " ! " " ! " ! ! ! " ! ! ! ' ' $ " ! " ! " ! & & ! " $ " ! ' ' % $ ' $ ' $ ' $ ' $ ' $ ' ' $ ' $ (# $ (# $ (# $ ' $ ' & $ ' & $ ' & $ ' & $ ' $ & & & $ ' ' "$ ' ' ' ' ' ' ' ' ' ' ' ' ' & $ ' ' ' ' ' ' " $ ' "$ ' "$ ' ' ' " $ ' "$ $ ' %$ ' % ' % ' % ' $ ' % ! ' % ' $ ' $ ' $ ' $ ' ' % $ ' $ ' ' ' ' ' ' ' ' ' ' ' ' ' ' % % ' ' ' ' ' ' ' ' ' ' ' $ ' & $ ' ' ' ' ' & $ ' % ' $ ' #$ ' ' # ' ' ' $ ' $ ' ' ' ' ' ' ' ' ' ' ' $ ' #( ' % " ! " ! " ! " ! " " $ " ! " ! " ! " ! " ! " ! ! (# $ ' ' ' & ' ' ' " $ ' $ " ! ! ' ' ' 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 40 order number: 305433, revision: 002 figure 5. intel ? 80333 i/o processor ballout ? right side (bottom view) b1240-02 16 17 18 19 20 21 22 23 24 25 26 27 28 29 16 17 18 19 20 21 22 23 24 25 26 27 28 29 af ae ad aj ah ag ac ab aa y w v u t r p n m l k j h g f e d c b a m_ck0 odt0 sclk gpio [6] gpio [5] gpio [0] gpio [4] a_ rcomp a_ clko0 a_ req64# a_ c/be7# dq[35] dq[40] dqs[8] dq[36] dq[38] dq[39] dq[34] dq[37] dq[32] dq[33] dq[53] dq[62] dq[49] vcc25 dm[6] dq[43] dq[42] dqs5 dq[54] dq[50] dq[57] dq[63] dqs5# dqs6 dqs#6 ba[0] ma10 cb[6] cb[2] cb[7] m_ck2# m_ck2 m_ck0# cb[3] dqs8# dqs[4] dqs4# dm[4] vss nb nb vss nb nb nb nb vss vss vss vcc25 vss vss vss vss vss vss vss vss vss cs1# vss vss vss vss vss dq[55] dm[5] dm[7] ma13 vss vcc25 vcc25 odt1 cs0# we# vss ddr res1 gpio [2] gpio [3] gpio [7] gpio [1] ddr cres0 a[16] ad[0] ddrslw cres ddrimp cres a[20] ddr res2 a[1] vcc25 vss vss vcc15 vcc25 vcc25 vcc25 vss vss vss vcc15 ras# vcc25 vcc25 sdta vcc25 vcc25 vcc15 vss vss vss vss ale a[21] ad[1] vcc15 vss vss vcc15 vcc15 vss vss ad[10] ad[4] ad[3] ad[13] ad[8] ad[5] ad[49] ad[51] a_ ad52 a_ ad57 a_ ad61 ad[54] a[0] scl0 ad[7] ad[6] a_rst# a_ gnt2# a_ gnt3# a[18] ad[14] ad[12] xint2# a[2] a[22] a[19] poe# pwe# ad[15] ad[11] ad[2] a[17] ad[9] scd0 cas# a_ pcixcap a_ ad50 xint#0 xint1# a_ ad48 vss vcc15 vcc15 vss vss vss vss vcc33 pce1# pce0# vcc33 vcc33 vcc33 vcc33 vss vssa4 vcc15 vss vcc33 vcc33 vss vcc15 vss vss vss vcc15 vcc33 vcc33 xint3# vcc33 vcc15 vss vss vcc33 vcc33 vcc33 vss vss vss vcc15 vss vss vcc33 vss vss vcc33 vcc33 vcc33 vss vss vss vcc15 vss vssa1 vss vss vcc15e vss vss a_ c/be1# a_ c/be2# a_ c/be3# a_ lock# a_ c/be6# a_ c/be5# a_ ack64# a_ c/be0# a_ ad14 a_ ad15 a_ ad9 a_ ad10 a_ ad13 a_ ad12 a_ ad30 a_ ad31 a_ ad25 a_ ad26 a_ ad1 a_ ad46 a_ clko3 a_ ad2 a_ ad37 a_ ad32 a_ ad39 a_ gnt0# a_ ad17 a_ ad18 a_ ad19 a_ ad6 a_ ad35 a_ ad38 a_ ad41 a_ ad42 a_ ad47 a_ ad3 a_ ad4 a_ ad5 a_ ad27 a_ ad28 a_ ad29 a_ ad7 a_ ad8 a_ ad11 vcc15e vss vss vss vss vss vss vss vcc33 vcc33 vcc33 vss a_ serr# vss vss vss vss vss vss vss vss vcc15e vss vss vss vss vcc33 vcc33 vcc33 vss vcc33 vcc33 a_par vcc33 vcc33 vss a_ clko1 a_ clko2 a_ clkout a_ perr# a_ devsel# vss a_ clkin vss vss vss vss vss vcc15 vcc pll1 a_ ad53 a_ ad33 vss a_ ad55 a_ ad34 vcc33 a_ ad60 a_ ad36 a_ ad62 a_ad0 a_ irdy# a_ req2# a_ ad24 a_ ad22 a_ ad16 pe_ icompi a_ ad21 a_ frame# a_ stop# a_ trdy# a_ req1# a_ad23 a_ m66en a_ ad20 a_ ad45 a_ ad44 pe0tn7 pe0tp7 pe0rp4 pe0rn4 pe0rn5 pe0rn6 pe0rn7 pe0rp7 pe0rp5 pe0rp6 pe0tn6 pe0tp4 pe0tp6 pe0tp5 pe0tn4 pe0tn5 a_ gnt1# vss a_ req3# a_ req0# a_ pme# a_ c/be4# a_ par64 a_ ad43 a_ ad40 a_ ad63 a_ ad59 a_ ad58 a_ ad56 vcc33 vcc33 vss vcc15 vss vss vss vss vcc15 vcc33 dq[45] dq[61] dq[41] dq[46] dq[47] dq[48] dq[52] dq[51] dq[56] dq[59] dq[58] dqs7 dqs7# dq[60] dq[44] vcc25 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 41 table 19. 829-lead package ? alphabetical ball listings (sheet 1 of 7) ball signal ball signal ball signal a1 -- b13 vss c25 a_ad21 a2 -- b14 vss c26 a_ad17 a3 vss b15 pe_rcompo c27 a_c/be2# a4 b_ad16 b16 vss c28 a_frame# a5 b_ad18 b17 pe0tn4 c29 vcc33 a6 b_ad21 b18 pe0rn6 d1 b_ad10 a7 b_c/be3# b19 vss d2 b_ad11 a8 b_ad26 b20 vss d3 b_ad12 a9 b_ad29 b21 a_ad30 d4 vcc33 a10 vss b22 vss d5 b_c/be2# a11 pe0rp2 b23 a_ad26 d6 b_ad19 a12 pe0rn2 b24 a_gnt1# d7 vss a13 vcc15e b25 vss d8 b_ad24 a14 pe_vssbg b26 a_ad18 d9 b_ad27 a15 pe_vccbg b27 a_ad16 d10 vss a16 pe_icompi b28 vss d11 pe0tn2 a17 vss b29 -- d12 pe0rn1 a18 pe0rp6 c1 vcc33 d13 vss a19 pe0tp6 c2 b_ad13 d14 pe0rp3 a20 pe0tn6 c3 b_ad14 d15 pe0tn3 a21 a_ad31 c4 b_par d16 pe0rp4 a22 a_ad29 c5 b_ad17 d17 vss a23 a_gnt0# c6 vcc33 d18 pe0rn5 a24 a_ad24 c7 b_ad22 d19 pe0tp5 a25 a_ad22 c8 b_ad25 d20 vss a26 a_ad19 c9 vcc33 d21 a_ad8 a27 vss c10 b_ad30 d22 a_ad27 a28 -- c11 pe0tp2 d23 vss a29 -- c12 pe0tp1 d24 a_ad23 b1 -- c13 vcc15e d25 a_ad20 b2 vss c14 pe0rn3 d26 vcc33 b3 b_ad15 c15 vss d27 a_c/be3# b4 b_c/be1# c16 pe0rn4 d28 a_stop# b5 vss c17 pe0tp4 d29 vss b6 b_ad20 c18 vcc15e e1 b_c/be0# b7 b_ad23 c19 pe0tn5 e2 vss b8 vss c20 a_m66en e3 b_m66en b9 b_ad28 c21 vcc33 e4 b_ad9 b10 b_ad31 c22 a_ad28 e5 vss b11 vss c23 a_ad25 e6 b_frame# b12 pe0tn1 c24 vcc33 e7 b_clkout 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 42 order number: 305433, revision: 002 e8 vss f20 a_ad9 h3 b_ad1 e9 vcc33 f21 vcc33 h4 b_ad2 e10 vss f22 a_ad5 h5 vcc33 e11 vss f23 a_ad1 h6 b_ack64# e12 pe0rp1 f24 vss h7 b_clko4 e13 pe0tn0 f25 a_clko2 h8 b_clko2 e14 vcc15e f26 a_par h9 b_clko3 e15 pe0tp3 f27 vss h10 b_trdy# e16 vcc15e f28 a_req1# h11 b_gnt2# e17 pe0rp7 f29 a_devsel# h12 b_gnt4# e18 pe0rp5 g1 b_ad3 h13 b_pme# e19 vss g2 b_ad4 h14 vss e20 a_ad10 g3 b_ad5 h15 refclk+ e21 a_req2# g4 vss h16 vss e22 vss g5 b_devsel# h17 a_c/be1# e23 a_ad2 g6 b_stop# h18 a_ad14 e24 a_ad0 g7 vss h19 a_ad11 e25 vss g8 vss h20 a_c/be0# e26 a_serr# g9 b_clkin h21 a_ad6 e27 a_lock# g10 vcc33 h22 a_ad3 e28 a_trdy# g11 b_req64# h23 a_clko3 e29 a_irdy# g12 b_req2# h24 a_clko0 f1 b_ad6 g13 vss h25 vss f2 b_ad7 g14 pe0rp0 h26 vcc33 f3 vcc33 g15 refclk- h27 vss f4 b_ad8 g16 pe0tn7 h28 vss f5 b_irdy# g17 vss h29 vss f6 vcc33 g18 a_ad15 j1 b_ad49 f7 b_clko0 g19 a_ad12 j2 b_ad48 f8 vss g20 vss j3 vcc33 f9 vss g21 a_ad7 j4 b_perr# f10 vss g22 a_ad4 j5 b_serr# f11 b_gnt3# g23 vcc33 j6 vss f12 vss g24 a_clko1 j7 b_lock# f13 pe0tp0 g25 a_clkout j8 b_clko1 f14 pe0rn0 g26 vss j9 vss f15 vss g27 a_clkin j10 vcc15 f16 pe0tp7 g28 vss j11 vss f17 pe0rn7 g29 a_perr# j12 vcc15 f18 vss h1 b_ad0 j13 vss f19 a_ad13 h2 vss j14 vcc15e table 19. 829-lead package ? alphabetical ball listings (sheet 2 of 7) ballsignalballsignalballsignal 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 43 j15 vss k27 a_c/be4# m10 vss j16 vcc15e k28 a_c/be5# m11 vccpll2 j17 vss k29 a_par64 m12 vssa2 j18 vcc33 l1 b_ad53 m13 vcc15 j19 vss l2 vss m14 vss j20 vcc33 l3 b_ad52 m15 vcc15 j21 vss l4 b_ad51 m16 vss j22 a_ad47 l5 vcc33 m17 vcc15 j23 a_ad46 l6 b_ad35 m18 vssa1 j24 vcc33 l7 b_ad34 m19 vccpll1 j25 a_ad45 l8 b_ad33 m20 vss j26 a_ad44 l9 vss m21 vcc33 j27 vcc33 l10 vcc15 m22 a_ad38 j28 a_ack64# l11 vss m23 a_ad37 j29 a_req64# l12 vcc15 m24 vss k1 b_ad50 l13 vss m25 a_ad36 k2 b_req4# l14 vss m26 a_ad62 k3 b_req3# l15 vccpll3 m27 vcc33 k4 vss l16 vss m28 a_ad61 k5 b_req1# l17 vss m29 a_ad60 k6 n/c7 l18 vcc15 n1 b_ad59 k7 vss l19 vss n2 b_ad58 k8 b_ad32 l20 vcc33 n3 b_ad57 k9 vcc15 l21 vss n4 vss k10 vcc15 l22 a_ad41 n5 b_ad41 k11 vcc15 l23 a_ad39 n6 b_ad40 k12 vss l24 a_ad40 n7 vss k13 vcc15 l25 vcc33 n8 b_ad39 k14 vss l26 a_c/be6# n9 vss k15 vssa3 l27 a_c/be7# n10 vcc15 k16 vss l28 vss n11 vss k17 vcc33 l29 a_ad63 n12 vcc15 k18 vss m1 b_ad56 n13 vss k19 vcc33 m2 b_ad55 n14 vcc15 k20 vss m3 vcc33 n15 vss k21 vcc33 m4 b_ad54 n16 vcc15 k22 a_ad42 m5 b_ad38 n17 vss k23 vss m6 vcc33 n18 vcc15 k24 a_ad43 m7 b_ad37 n19 vss k25 a_req3# m8 b_ad36 n20 vcc33 k26 vss m9 vcc15 n21 vss table 19. 829-lead package ? alphabetical ball listings (sheet 3 of 7) ball signal ball signal ball signal 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 44 order number: 305433, revision: 002 n22 a_ad35 r5 b_ad45 t17 vcc15 n23 vcc33 r6 vcc33 t18 vss n24 a_ad34 r7 b_ad46 t19 vcc15 n25 a_req0# r8 b_ad47 t20 vss n26 vcc33 r9 vss t21 ad10 n27 a_ad59 r10 vcc15 t22 ad6 n28 a_ad57 r11 vss t23 ad4 n29 a_ad58 r12 vcc15 t24 xint2# p1 b_ad60 r13 vss t25 vss p2 vss r14 vcc15 t26 a_ad49 p3 b_ad61 r15 vccpll4 t27 a_ad50 p4 b_ad62 r16 vssa4 t28 vss p5 vss r17 vss t29 a_rcomp p6 b_ad44 r18 vcc15 u1 b_c/be4# p7 b_ad43 r19 vss u2 b_c/be5# p8 b_ad42 r20 vcc33 u3 b_c/be7# p9 vcc15 r21 a_pcixcap u4 vss p10 vss r22 a_rst# u5 b_hprsnt1# p11 vcc15 r23 xint3# u6 b_hatnled# p12 vss r24 vcc33 u7 vcc33 p13 vccpll5 r25 a_pme# u8 b_hpwrflt# p14 vssa5 r26 a_ad51 u9 vss p15 vcc15 r27 vcc33 u10 vcc15 p16 vss r28 a_ad52 u11 vss p17 vcc15 r29 a_ad53 u12 vcc13 p18 vss t1 n/c2 u13 vss p19 vcc15 t2 vss u14 vcc15 p20 vss t3 b_c/be6# u15 vss p21 vcc33 t4 b_gnt1# u16 vcc15 p22 a_gnt2# t5 vss u17 vss p23 a_ad32 t6 b_gnt0# u18 vcc15 p24 a_ad33 t7 vss u19 vss p25 vss t8 b_hmrl# u20 vcc33 p26 a_ad54 t9 vcc15 u21 a18 p27 a_ad55 t10 vss u22 ad14 p28 vss t11 vcc15 u23 vss p29 a_ad56 t12 vss u24 ad12 r1 b_ad63 t13 vcc15 u25 a_gnt3# r2 b_par64 t14 vss u26 vcc33 r3 vcc33 t15 vcc15 u27 xint0# r4 b_req0# t16 vss u28 xint1# table 19. 829-lead package ? alphabetical ball listings (sheet 4 of 7) ballsignalballsignalballsignal 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 45 u29 a_ad48 w12 vcc13 y24 ad11 v1 b_rcomp w13 vss y25 a0 v2 xint7# w14 vcc15 y26 vcc33 v3 vcc33 w15 vss y27 a17 v4 xint6# w16 vcc15 y28 a21 v5 xint5# w17 vss y29 a20 v6 vss w18 vcc15 aa1 b_hbutton# v7 b_hpwrled# w19 vss aa2 n/c4 v8 b_rst# w20 vcc33 aa3 vss v9 vcc15 w21 a2 aa4 n/c5 v10 vss w22 a22 aa5 trst# v11 vcc15 w23 ad7 aa6 vss v12 vss w24 ad2 aa7 pwrgd v13 vcc13 w25 vss aa8 hpi# v14 vss w26 ad8 aa9 vss v15 vcc15 w27 ad9 aa10 vcc25 v16 vss w28 vss aa11 vss v17 vcc15 w29 a16 aa12 vcc25 v18 vss y1 vcc15 aa13 vss v19 vcc15 y2 tck aa14 vcc25 v20 vss y3 vss aa15 vss v21 poe# y4 vss aa16 vcc25 v22 a19 y5 n/c0 aa17 vss v23 ad3 y6 tdi aa18 vcc25 v24 vcc33 y7 vss aa19 vss v25 ad13 y8 n/c3 aa20 vcc25 v26 ad5 y9 vcc13 aa21 gpio2/u0_cts# v27 vss y10 vss aa22 gpio3/u0_rts# v28 ad1 y11 vcc13 aa23 scl0 v29 ad0 y12 vss aa24 vcc33 w1 pwrdelay y13 vcc13 aa25 pce1# w2 vss y14 vss aa26 pce0# w3 xint4# y15 vcc15 aa27 vss w4 b_pcixcap y16 vss aa28 ale w5 vcc33 y17 vcc15 aa29 a1 w6 b_hreset# y18 vss ab1 n/c6 w7 b_hpwren y19 vcc15 ab2 vss w8 b_hprsnt2# y20 vss ab3 tdo w9 vss y21 pwe# ab4 tms w10 vcc13 y22 ad15 ab5 vss w11 vss y23 vss ab6 rstin# table 19. 829-lead package ? alphabetical ball listings (sheet 5 of 7) ball signal ball signal ball signal 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 46 order number: 305433, revision: 002 ab7 vcc25 ac19 ras# ae2 vss ab8 vss ac20 vcc25 ae3 dqs0# ab9 vcc25 ac21 cas# ae4 dqs0 ab10 vss ac22 odt0 ae5 vss ab11 vcc25 ac23 vss ae6 dq13 ab12 vss ac24 sdta/scd1 ae7 dq8 ab13 vcc25 ac25 gpio5/u1_txd ae8 vss ab14 vss ac26 gpio4/u1_rxd ae9 dqs2# ab15 vcc25 ac27 ddrcres0 ae10 dq23 ab16 vss ac28 ddrslwcres ae11 vss ab17 vcc25 ac29 ddrimpcres ae12 ma1 ab18 vss ad1 dq5 ae13 dq26 ab19 vcc25 ad2 dq4 ae14 vss ab20 odt1 ad3 vss ae15 cb0 ab21 scd0 ad4 dq1 ae16 vss ab22 sclk/scl1 ad5 dq0 ae17 cb7 ab23 gpio6/u1_cts# ad6 vcc25 ae18 dq33 ab24 gpio7/u1_rts# ad7 ma7 ae19 vss ab25 vss ad8 dq12 ae20 cs0# ab26 gpio0/u0_rxd ad9 vss ae21 dm5 ab27 gpio1/u0_txd ad10 dq22 ae22 vss ab28 ddrres1 ad11 dq19 ae23 dq53 ab29 ddrres2 ad12 vcc25 ae24 dq52 ac1 ddr_vref ad13 ba1 ae25 vss ac2 vss ad14 dq27 ae26 dq57 ac3 vss ad15 vss ae27 dm7 ac4 vss ad16 cb6 ae28 vss ac5 vss ad17 cb2 ae29 dqs7 ac6 vss ad18 ba0 af1 dq6 ac7 vss ad19 vcc25 af2 dq7 ac8 ma11 ad20 we# af3 dq2 ac9 ma9 ad21 vss af4 vcc25 ac10 vcc25 ad22 ma13 af5 ma12 ac11 vss ad23 cs1# af6 dq9 ac12 ma2 ad24 vcc25 af7 vss ac13 ma0 ad25 dq62 af8 dq21 ac14 cb5 ad26 dq63 af9 dqs2 ac15 cb4 ad27 vss af10 vcc25 ac16 cb3 ad28 dq59 af11 ma3 ac17 vss ad29 dq58 af12 dq29 ac18 ma10 ae1 dm0 af13 vcc25 table 19. 829-lead package ? alphabetical ball listings (sheet 6 of 7) ballsignalballsignalballsignal 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 47 af14 dq30 ag26 dq50 aj9 dm2 af15 cb1 ag27 dq51 aj10 ma8 af16 dqs_8# ag28 dq60 aj11 dq28 af17 vcc25 ag29 vss aj12 dq25 af18 dq32 ah1 -- aj13 dm3 af19 dqs4 ah2 vss aj14 m_ck1 af20 vcc25 ah3 m_rst# aj15 m_ck1# af21 dq45 ah4 cke1 aj16 m_ck0 af22 vcc25 ah5 vss aj17 m_ck0# af23 dq43 ah6 dq14 aj18 dq36 af24 dq48 ah7 dq20 aj19 dm4 af25 dq49 ah8 vss aj20 dq38 af26 vcc25 ah9 ma6 aj21 dq35 af27 dq61 ah10 ma5 aj22 dq40 af28 dq56 ah11 vcc25 aj23 dqs5# af29 dqs7# ah12 dq24 aj24 dq46 ag1 vss ah13 dqs3# aj25 dqs6# ag2 dq3 ah14 vss aj26 dqs6 ag3 vss ah15 dm8 aj27 vss ag4 cke0 ah16 vcc25 aj28 -- ag5 dm1 ah17 m_ck2 aj29 -- ag6 vss ah18 dq37 ag7 dq11 ah19 vss ag8 dq16ah20dq39 ag9 vss ah21 dq44 ag10 dq18 ah22 vss ag11 ma4 ah23 dqs5 ag12 vss ah24 dq47 ag13 dqs3 ah25 vss ag14 dq31 ah26 dq54 ag15 vss ah27 dq55 ag16 dqs8 ah28 vss ag17 m_ck2# ah29 -- ag18 vss aj1 -- ag19 dqs4# aj2 -- ag20 dq34 aj3 vcc25 ag21 vss aj4 dqs1# ag22 dq41 aj5 dqs1 ag23 dq42 aj6 dq15 ag24 vss aj7 dq10 ag25 dm6 aj8 dq17 table 19. 829-lead package ? alphabetical ball listings (sheet 7 of 7) ball signal ball signal ball signal 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 48 order number: 305433, revision: 002 table 20. 829-lead package ? alphabetical signal listings (sheet 1 of 7) signal ball signal ball signal ball -- a1 a_ad28 c22 a_c/be5# k28 -- a2 a_ad29 a22 a_c/be6# l26 -- a28 a_ad30 b21 a_c/be7# l27 -- a29 a_ad31 a21 a_clkin g27 -- ah1 a_ad32 p23 a_clko0 h24 -- ah29 a_ad33 p24 a_clko1 g24 -- aj1 a_ad34 n24 a_clko2 f25 -- aj2 a_ad35 n22 a_clko3 h23 -- aj28 a_ad36 m25 a_clkout g25 -- aj29 a_ad37 m23 a_devsel# f29 -- b1 a_ad38 m22 a_frame# c28 -- b29 a_ad39 l23 a_gnt0# a23 a_ack64# j28 a_ad40 l24 a_gnt1# b24 a_ad0 e24 a_ad41 l22 a_gnt2# p22 a_ad1 f23 a_ad42 k22 a_gnt3# u25 a_ad2 e23 a_ad43 k24 a_irdy# e29 a_ad3 h22 a_ad44 j26 a_lock# e27 a_ad4 g22 a_ad45 j25 a_m66en c20 a_ad5 f22 a_ad46 j23 a_par f26 a_ad6 h21 a_ad47 j22 a_par64 k29 a_ad7 g21 a_ad48 u29 a_pcixcap r21 a_ad8 d21 a_ad49 t26 a_perr# g29 a_ad9 f20 a_ad50 t27 a_pme# r25 a_ad10 e20 a_ad51 r26 a_rcomp t29 a_ad11 h19 a_ad52 r28 a_req0# n25 a_ad12 g19 a_ad53 r29 a_req1# f28 a_ad13 f19 a_ad54 p26 a_req2# e21 a_ad14 h18 a_ad55 p27 a_req3# k25 a_ad15 g18 a_ad56 p29 a_req64# j29 a_ad16 b27 a_ad57 n28 a_rst# r22 a_ad17 c26 a_ad58 n29 a_serr# e26 a_ad18 b26 a_ad59 n27 a_stop# d28 a_ad19 a26 a_ad60 m29 a_trdy# e28 a_ad20 d25 a_ad61 m28 a0 y25 a_ad21 c25 a_ad62 m26 a1 aa29 a_ad22 a25 a_ad63 l29 a2 w21 a_ad23 d24 a_c/be0# h20 a16 w29 a_ad24 a24 a_c/be1# h17 a17 y27 a_ad25 c23 a_c/be2# c27 a18 u21 a_ad26 b23 a_c/be3# d27 a19 v22 a_ad27 d22 a_c/be4# k27 a20 y29 a21 y28 b_ad21 a6 b_ad62 p4 a22 w22 b_ad22 c7 b_ad63 r1 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 49 ad0 v29 b_ad23 b7 b_c/be0# e1 ad1 v28 b_ad24 d8 b_c/be1# b4 ad2 w24 b_ad25 c8 b_c/be2# d5 ad3 v23 b_ad26 a8 b_c/be3# a7 ad4 t23 b_ad27 d9 b_c/be4# u1 ad5 v26 b_ad28 b9 b_c/be5# u2 ad6 t22 b_ad29 a9 b_c/be6# t3 ad7 w23 b_ad30 c10 b_c/be7# u3 ad8 w26 b_ad31 b10 b_clkin g9 ad9 w27 b_ad32 k8 b_clko0 f7 ad10 t21 b_ad33 l8 b_clko1 j8 ad11 y24 b_ad34 l7 b_clko2 h8 ad12 u24 b_ad35 l6 b_clko3 h9 ad13 v25 b_ad36 m8 b_clko4 h7 ad14 u22 b_ad37 m7 b_clkout e7 ad15 y22 b_ad38 m5 b_devsel# g5 ale aa28 b_ad39 n8 b_frame# e6 b_ack64# h6 b_ad40 n6 b_gnt0# t6 b_ad0 h1b_ad41n5b_gnt1#t4 b_ad1 h3 b_ad42 p8 b_gnt2# h11 b_ad2 h4 b_ad43 p7 b_gnt3# f11 b_ad3 g1 b_ad44 p6 b_gnt4# h12 b_ad4 g2 b_ad45 r5 b_hpwrflt# u8 b_ad5 g3 b_ad46 r7 b_hprsnt2# w8 b_ad6 f1 b_ad47 r8 b_hmrl# t8 b_ad7 f2 b_ad48 j2 b_hpwren w7 b_ad8 f4 b_ad49 j1 b_hpwrled# v7 b_ad9 e4 b_ad50 k1 b_hprsnt1# u5 b_ad10 d1 b_ad51 l4 b_hatnled# u6 b_ad11 d2 b_ad52 l3 b_hbutton# aa1 b_ad12 d3 b_ad53 l1 b_irdy# f5 b_ad13 c2 b_ad54 m4 b_lock# j7 b_ad14 c3 b_ad55 m2 b_m66en e3 b_ad15 b3 b_ad56 m1 b_par c4 b_ad16 a4 b_ad57 n3 b_par64 r2 b_ad17 c5 b_ad58 n2 b_pcixcap w4 b_ad18 a5 b_ad59 n1 b_perr# j4 b_ad19 d6 b_ad60 p1 b_pme# h13 b_ad20 b6 b_ad61 p3 b_rcomp v1 table 20. 829-lead package ? alphabetical signal listings (sheet 2 of 7) signal ball signal ball signal ball 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 50 order number: 305433, revision: 002 b_req0# r4 dq1 ad4 dq42 ag23 b_req1# k5 dq2 af3 dq43 af23 b_req2# g12 dq3 ag2 dq44 ah21 b_req3# k3 dq4 ad2 dq45 af21 b_req4# k2 dq5 ad1 dq46 aj24 b_req64# g11 dq6 af1 dq47 ah24 b_rst# v8 dq7 af2 dq48 af24 b_serr# j5 dq8 ae7 dq49 af25 b_stop# g6 dq9 af6 dq50 ag26 b_trdy# h10 dq10 aj7 dq51 ag27 ba0 ad18 dq11 ag7 dq52 ae24 ba1 ad13 dq12 ad8 dq53 ae23 cas# ac21 dq13 ae6 dq54 ah26 cb0 ae15 dq14 ah6 dq55 ah27 cb1 af15 dq15 aj6 dq56 af28 cb2 ad17 dq16 ag8 dq57 ae26 cb3 ac16 dq17 aj8 dq58 ad29 cb4 ac15 dq18 ag10 dq59 ad28 cb5 ac14 dq19 ad11 dq60 ag28 cb6 ad16 dq20 ah7 dq61 af27 cb7 ae17 dq21 af8 dq62 ad25 cke0 ag4 dq22 ad10 dq63 ad26 cke1 ah4 dq23 ae10 dqs0 ae4 cs0# ae20 dq24 ah12 dqs0# ae3 cs1# ad23 dq25 aj12 dqs1 aj5 ddr_vref ac1 dq26 ae13 dqs2 af9 ddrcres0 ac27 dq27 ad14 dqs3 ag13 ddrimpcres ac29 dq28 aj11 dqs4 af19 ddrres1 ab28 dq29 af12 dqs5 ah23 ddrres2 ab29 dq30 af14 dqs6 aj26 ddrslwcres ac28 dq31 ag14 dqs7 ae29 dm0 ae1 dq32 af18 dqs8 ag16 dm1 ag5 dq33 ae18 dqs1# aj4 dm2 aj9 dq34 ag20 dqs2# ae9 dm3 aj13dq35aj21dqs3#ah13 dm4 aj19dq36aj18dqs4#ag19 dm5 ae21 dq37 ah18 dqs5# aj23 dm6 ag25 dq38 aj20 dqs6# aj25 dm7 ae27 dq39 ah20 dqs7# af29 dm8 ah15 dq40 aj22 dqs_8# af16 dq0 ad5 dq41 ag22 gpio0/u0_rxd ab26 table 20. 829-lead package ? alphabetical signal listings (sheet 3 of 7) signal ball signal ball signal ball 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 51 gpio1/u0_txd ab27 pe_icompi a16 refclk- g15 gpio2/u0_cts# aa21 pe_rcompo b15 refclk+ h15 gpio3/u0_rts# aa22 pe_vccbg a15 rstin# ab6 gpio4/u1_rxd ac26 pe_vssbg a14 scd0 ab21 gpio5/u1_txd ac25 pe0rn0 f14 scd1/sdta ac24 gpio6/u1_cts# ab23 pe0rn1 d12 scl0 aa23 gpio7/u1_rts# ab24 pe0rn2 a12 scl1/sclk ab22 hpi# aa8 pe0rn3 c14 tck y2 m_ck0 aj16 pe0rn4 c16 tdi y6 m_ck1 aj14 pe0rn5 d18 tdo ab3 m_ck2 ah17 pe0rn6 b18 tms ab4 m_ck0# aj17 pe0rn7 f17 trst# aa5 m_ck1# aj15 pe0rp0 g14 vcc13 u12 m_ck2# ag17 pe0rp1 e12 vcc13 v13 m_rst# ah3 pe0rp2 a11 vcc13 w10 ma0 ac13 pe0rp3 d14 vcc13 w12 ma1 ae12 pe0rp4 d16 vcc13 y9 ma2 ac12 pe0rp5 e18 vcc13 y11 ma3 af11 pe0rp6 a18 vcc13 y13 ma4 ag11 pe0rp7 e17 vcc15e a13 ma5 ah10 pe0tn0 e13 vcc15e c13 ma6 ah9 pe0tn1 b12 vcc15e c18 ma7 ad7 pe0tn2 d11 vcc15e e14 ma8 aj10 pe0tn3 d15 vcc15e e16 ma9 ac9 pe0tn4 b17 vcc15e j14 ma10 ac18 pe0tn5 c19 vcc15e j16 ma11 ac8 pe0tn6 a20 vcc15 j10 ma12 af5 pe0tn7 g16 vcc15 j12 ma13 ad22 pe0tp0 f13 vcc15 k9 n/c0 y5 pe0tp1 c12 vcc15 k10 b_hreset# w6 pe0tp2 c11 vcc15 k11 n/c2 t1 pe0tp3 e15 vcc15 k13 n/c3 y8 pe0tp4 c17 vcc15 l10 n/c4 aa2 pe0tp5 d19 vcc15 l12 n/c5 aa4 pe0tp6 a19 vcc15 l18 n/c6 ab1 pe0tp7 f16 vcc15 m9 n/c7 k6 poe# v21 vcc15 m13 odt0 ac22 pwe# y21 vcc15 m15 odt1 ab20 pwrdelay w1 vcc15 m17 pce0# aa26 pwrgd aa7 vcc15 n10 pce1# aa25 ras# ac19 vcc15 n12 table 20. 829-lead package ? alphabetical signal listings (sheet 4 of 7) signal ball signal ball signal ball 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 52 order number: 305433, revision: 002 vcc15 n14 vcc25 aa20 vcc33 j24 vcc15 n16 vcc25 ab11 vcc33 j27 vcc15 n18 vcc25 ab13 vcc33 k17 vcc15 p9 vcc25 ab15 vcc33 k19 vcc15 p11 vcc25 ab17 vcc33 k21 vcc15 p15 vcc25 ab19 vcc33 l5 vcc15 p17 vcc25 ac10 vcc33 l20 vcc15 p19 vcc25 ac20 vcc33 l25 vcc15 r10 vcc25 ad6 vcc33 m3 vcc15 r12 vcc25 ad12 vcc33 m6 vcc15 r14 vcc25 ad19 vcc33 m21 vcc15 r18 vcc25 ad24 vcc33 m27 vcc15 t9 vcc25 af4 vcc33 n20 vcc15 t11 vcc25 af10 vcc33 n23 vcc15 t13 vcc25 af13 vcc33 n26 vcc15 t15 vcc25 af17 vcc33 p21 vcc15 t17 vcc25 af20 vcc33 r3 vcc15 t19 vcc25 af22 vcc33 r6 vcc15 u10 vcc25 af26 vcc33 r20 vcc15 u14 vcc25 ah11 vcc33 r24 vcc15 u16 vcc25 ah16 vcc33 r27 vcc15 u18 vcc25 aj3 vcc33 u7 vcc15 v9 vcc33 c1 vcc33 u20 vcc15 v11 vcc33 c6 vcc33 u26 vcc15 v15 vcc33 c9 vcc33 v24 vcc15 v17 vcc33 c21 vcc33 v3 vcc15 v19 vcc33 c24 vcc33 w5 vcc15 w14 vcc33 c29 vcc33 w20 vcc15 w16 vcc33 d4 vcc33 y26 vcc15 w18 vcc33 d26 vcc33 aa24 vcc15 y1 vcc33 e9 vccpll1 m19 vcc15 y15 vcc33 f3 vccpll2 m11 vcc15 y17 vcc33 f6 vccpll3 l15 vcc15 y19 vcc33 f21 vccpll4 r15 vcc25 ab7 vcc33 g10 vccpll5 p13 vcc25 ab9 vcc33 g23 vss a3 vcc25 aa10 vcc33 h5 vss a10 vcc25 aa12 vcc33 h26 vss a17 vcc25 aa14 vcc33 j3 vss a27 vcc25 aa16 vcc33 j18 vss b2 vcc25 aa18 vcc33 j20 vss b5 table 20. 829-lead package ? alphabetical signal listings (sheet 5 of 7) signal ball signal ball signal ball 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 53 vss b8 vss g28 vss n7 vss b11 vss h2 vss n9 vss b13 vss h14 vss n11 vss b14 vss h16 vss n13 vss b16 vss h25 vss n15 vss b19 vss h27 vss n17 vss b20 vss h28 vss n19 vss b22 vss h29 vss n21 vss b25 vss j6 vss p2 vss b28 vss j9 vss p5 vss c15 vss j11 vss p10 vss d7 vss j13 vss p12 vss d10 vss j15 vss p16 vss d13 vss j17 vss p18 vss d17 vss j19 vss p20 vss d20 vss j21 vss p25 vss d23 vss k4 vss p28 vss d29 vss k7 vss r9 vss e2 vss k12 vss r11 vss e5 vss k14 vss r13 vss e8 vss k16 vss r17 vss e10 vss k18 vss r19 vss e11 vss k20 vss t2 vss e19 vss k23 vss t5 vss e22 vss k26 vss t7 vss e25 vss l2 vss t10 vss f8 vss l9 vss t12 vss f9 vss l11 vss t14 vss f10 vss l13 vss t16 vss f12 vss l14 vss t18 vss f15 vss l16 vss t20 vss f18 vss l17 vss t25 vss f24 vss l19 vss t28 vss f27 vss l21 vss u4 vss g4 vss l28 vss u9 vss g7 vss m10 vss u11 vss g8 vss m14 vss u13 vss g13 vss m16 vss u15 vss g17 vss m20 vss u17 vss g20 vss m24 vss u19 vss g26 vss n4 vss u23 table 20. 829-lead package ? alphabetical signal listings (sheet 6 of 7) signal ball signal ball signal ball 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 54 order number: 305433, revision: 002 vss v6 vss ab14 vss ah8 vss v10 vss ab16 vss ah14 vss v12 vss ab18 vss ah19 vss v14 vss ab25 vss ah22 vss v16 vss ac2 vss ah25 vss v18 vss ac3 vss ah28 vss v20 vss ac4 vss aj27 vss v27 vss ac5 vssa1 m18 vss w2 vss ac6 vssa2 m12 vss w9 vss ac7 vssa3 k15 vss w11 vss ac11 vssa4 r16 vss w13 vss ac17 vssa5 p14 vss w15 vss ac23 we# ad20 vss w17 vss ad3 xint0# u27 vss w19 vss ad9 xint1# u28 vss w25 vss ad15 xint2# t24 vss w28 vss ad21 xint3# r23 vss y3 vss ad27 xint4# w3 vss y4 vss ae2 xint5# v5 vss y7 vss ae5 xint6# v4 vss y10 vss ae8 xint7# v2 vss y12 vss ae11 vss y14 vss ae14 vss y16 vss ae16 vss y18 vss ae19 vss y20 vss ae22 vss y23 vss ae25 vss aa3 vss ae28 vss aa6 vss af7 vss aa9 vss ag1 vss aa11 vss ag3 vss aa13 vss ag6 vss aa15 vss ag9 vss aa17 vss ag12 vss aa19 vss ag15 vss aa27 vss ag18 vss ab2 vss ag21 vss ab5 vss ag24 vss ab8 vss ag29 vss ab10 vss ah2 vss ab12 vss ah5 table 20. 829-lead package ? alphabetical signal listings (sheet 7 of 7) signal ball signal ball signal ball 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 55 3.2 package thermal specifications see intel ? 80333 i/o processor thermal design guidelines application note (306630). 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 56 order number: 305433, revision: 002 4.0 electrical specifications 4.1 absolute maximum ratings 4.2 v ccpll pin requirements the v ccpll[1-5] balls for the phase lock loop (pll) circuit must each have filters, and be connected to the appropriate vssa ball. see the intel ? 80333 i/o processor design guide for specific recommendations. table 21. absolute maximum ratings parameter maximum rating note: this data sheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product becomes available. the specific ations are subject to change without notice. contact your local intel representative before finalizing a design. storage temperature ?55 c to +125c case temperature under bias 0c to +95c supply voltage v cc33 wrt. v ss ?0.5 v to +4.1 v supply voltage v cc25 wrt. v ss ?0.5 v to +3.2 v supply voltage v cc15 wrt. v ss ?0.5 v to +2.1 v supply voltage v cc13 wrt. v ss ?0.5 v to +2.1 v voltage on any ball wrt. v ss ?0.5 v to v ccp + 0.5 v warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 22. operating conditions symbol parameter minimum maximum units notes v cc33 3.3 v pci/pci-x supply voltage 3.0 3.6 v 10% v cc25/18 2.5 v/1.8v ddr/ddr-ii supply voltage 2.3/1.7 2.7/1.9 v 8%, 5% 1 v cc15 1.5 v iop core supply voltage 1.425 1.575 v 5% 1 v cc13 1.35 v intel xscale ? core supply voltage 1.282 1.418 v 5% v ccpll1-5 pll supply voltage v cc15 v cc15 v ddr_vref memory i/o reference voltage 0.49 v cc25/18 0.51 v cc25/18 v pe_vccbg 2.5 v pci express* vcc band gap 2.375 2.625 5% refclk input clock frequency 100 -300 ppm 100 + 300 ppm mhz 100 mhz nominal t c case temperature under bias 0 95 c notes: 1. 3% dc; additional 2% for ac transients. under no circumstance may the supply voltage go past the ac min./max. window. the supply voltage window may go outside the dc min./max. window for transient events. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 57 4.3 targeted dc specifications table 23. dc characteristics symbol parameter minimum maximum units notes v il1 input low voltage (ddr sdram) -0.3 ddr_vref - 0.18 v ( 1 , 2 ) v ih1 input high voltage (ddr sdram) ddr_vref + 0.18 v cc25 + 0.3 v ( 1 , 2 ) v il2 input low voltage (ddr-ii sdram) -0.2 ddr_vref - 0.125 v ( 1 , 3 ) v ih2 input high voltage (ddr-ii sdram) ddr_vref + 0.125 v cc25 + 0.2 v ( 1 , 3 ) v il2 input low voltage (misc.) -0.3 0.8 v ( 4 , 5 ) v ih2 input high voltage (misc.) 2.0 v cc33 + 0.3 v ( 4 , 5 ) v il3 input low voltage (pci-x) -0.5 0.35 v cc33 v v ih3 input high voltage (pci-x/pci) 0.5 v cc33 v cc33 + 0.5 v v il5 input low voltage (pci) -0.5 0.3 v cc33 v v ol2 output low voltage (misc.) 0.4 v i ol = 6 ma v oh2 output high voltage (misc.) 2.4 v i oh = -2 ma v ol1 output low voltage (ddr sdram) 0.35 v i ol = 12.5 ma ( 1 , 2 ) v oh1 output high voltage (ddr sdram) 1.95 v i oh = -12.5 ma ( 1 , 2 ) v ol2 output low voltage (ddr-ii sdram) 0.414 v i ol = 20.7ma ( 3 ) v oh2 output high voltage (ddr-ii sdram) 1.314 v i oh = -18ma ( 3 ) v ol3 output low voltage (pci-x) 0.1 v cc33 v i ol = 1500 a v oh3 output high voltage (pci-x) 0.9 v cc33 v i oh = -500 a c in input pin capacitance 8 pf ( 6 ) c clk pci clock pin capacitance 8 pf ( 6 ) l pin ball inductance 15 nh ( 1 , 2 , 6 ) notes: 1. sdram signals include ma[12:0] , ba[1:0] , cas# , cs[1:0]# , cke[1:0] , dm[8:0] , ras# , we# , m_ck[2:0] , m_ck[2:0]# , dq[63:0] , dqs[8:0] and cb[7:0] . 2. for 2.5 v ddr sdram support. 3. for 1.8 v ddr-ii sdram support. 4. miscellaneous signals include all signals that are not pci-x or sdram signals. 5. includes pci-x express auxiliary signals; pwrgd 6. ensured by design. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 58 order number: 305433, revision: 002 table 24. i cc characteristics symbol parameter typ. max. units notes i li1 input leakage current for each signal except tck , tms , trst# , tdi 2 a 0 v in v cc (4) i li2 input leakage current for tck , tms , trst# , tdi -140 -250 a v in = 0.45 v ( 1 , 4) i cc33 active (power supply) power supply current - pci-x interfaces both at 66 mhz both at 100 mhz both at 133 mhz 1.33 1.20 1.04 a ( 1 , 2 ) i cc25 active (power supply) power supply current - ddr 0.580 a ( 1 , 2 ) i cc18 active (power supply) power supply current - ddr-ii 0.487 a ( 1 , 2 ) i cc15 active (power supply) power supply current - iop/bridge core 4.7 a ( 1 , 2 ) i cc13 active (power supply) power supply current - intel xscale ? core 800 mhz 667 mhz 500 mhz 0.453 0.411 0.358 a ( 1 , 2 ) i cc33 active (thermal) thermal current - pci-x interfaces both at 66 mhz both at 100 mhz both at 133 mhz 1.08 1.00 0.914 a ( 1 , 3 ) i cc25 active (thermal) thermal current - ddr 0.295 a ( 1 , 3 ) i cc18 active (thermal) thermal current - ddr-ii 0.255 a ( 1 , 3 ) i cc15 active (thermal) thermal current - iop/bridge core 3.8 a ( 1 , 3 ) i cc13 active (thermal) thermal current - intel xscale ? core 800 mhz 667 mhz 500 mhz 0.430 0.390 0.340 a ( 1 , 3 ) notes: 1. measured with device operating and outputs loaded to the test condition in figure 14, ?ac test load for all signals except pci and ddr sdram? on page 73 . 2. i cc active (power supply) value is provided for selecting the system power supply. this is based on the worst case data patterns and skew material at the following worst case voltages: v cc33 = 3.63 v, v cc25 = 2.7 v, v cc18 = 1.9v, v cc15 = 1.575 v, v cc13 = 1.41 v. 3. i cc active (thermal) value is provided for selecting the system thermal design power (tdp). this is based on the following typical voltages: v cc33 = 3.3 v, v cc25 = 2.5 v, v cc18 = 1.8v, v cc15 = 1.5 v, v cc13 = 1.35 v. 4. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 59 4.4 targeted ac specifications 4.4.1 clock signal timings table 25. pci clock timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max min. max t f1 pci clock frequency 100 133 66 100 50 66 33 66 16 33 mhz 1 t c1 pci clock cycle time - avg. absolute minimum 7.5101015152015303060 ns 1 7.375 9.875 14.8 14.8 29.7 ns 3,4 t ch1 pci clock high time 3 3 6 6 11 ns t cl1 pci clock low time 3 3 6 6 11 ns t sr1 pci clock slew rate 1.5 4 1.5 4 1.5 4 1.5 4 1 4 v/ns 2 pci spread spectrum requirements f mod pci clock modulation frequency 30 33 30 33 30 33 30 33 khz f spread pci clock frequency spread -1 0 -1 0 -1 0 -1 0 % notes: 1. clock frequency may not change beyond spread-spectrum limits except while rstin# is asserted or pwrgd deasserted. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. the minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. clock jitter class 2, per pci-x electr ical and mechanical rev 2.0a specification table 26. ddr clock timings symbol parameter ddr-ii 400 ddr333 units notes minimum maximum minimum maximum t f2 ddr sdram clock frequency 200 167 mhz t c2 ddr sdram clock cycle time 5.0 6.0/7.5 (1) ns t ch2 ddr sdram clock high time 2.15 2.7/3.37 (1) ns t cl2 ddr sdram clock lowtime 2.15 2.7/3.37 (1) ns t cs2 ddr sdram clock period stability 350 350 ps t skew2 ddr sdram clock skew for any differential clock pair ( m_ck[2:0] - m_ck[2:0]# ) 100 100 ps t skew3 ddr sdram clock skew for any clock pair and any system memory strobe ( m_ck - dqs ). -285 285 -285 285 ps 2 notes: 1. cl = 2.5/2.0. 2. this specification applies for writes only; that is, when the 80333 is driving the strobes as we ll as the clocks. refer to th e jedec specification for an explanation of strobe to clock timing for ddr reads. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 60 order number: 305433, revision: 002 table 27. pci express* clock timings symbol parameter minimum nominal maximum units notes t f2 pci express* clock frequency -300ppm 100 +300 ppm mhz 1 t c2 pci express* clock cycle time 10 10.2 ns 2 t ccj cycle to cycle jitter 200 ps clock duty cycle 45 55 % t rise refclk rise time across 600mv 300 600 ps 3 t fall refclk fall time across 600mv 300 600 ps 3 rise-fall matching 20 % 3,4 cross point at 1v 0.51 0.76 v rising edge ringback 0.85 v falling edge ringback 0.35 v notes: 1. spread spectrum clocking is allowed with the following three requirements; a. all device timings must be met including jitter, skew, min./max. clock period. output rise/fall timing must meet the existing non-spread spectrum specifications. b. all non-spread host and pci functionality must be mainta ined in the spread-spectrum mode (includes all power management functions). c. the minimum clock period cannot be violated. the pref erred method is to adjust the spread technique to allow for modulation above the nominal frequency. this technique is often called ?down-spreading?. 2. measured at crossing point. 3. measured from v ol = 0.2 v to v oh =0.8v. 4. determined as a fraction of 2 (trise - tfall)/(trise + tfall). 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 61 4.4.2 ddr/ddr-ii sdram interface signal timings table 28. ddr sdram signal timings symbol parameter minimum max. units notes t vb1 dq, cb and dm write output valid time before dqs. 2.68 ns ( 4 ) t va1 dq, cb and dm write output valid time after dqs. 2.68 ns ( 4 ) t vb3 address and command write output valid before m_ck rising edge. 2.62 ns ( 4 , 9 ) t va3 address and command write output valid after m_ck rising edge. 2.62 ns ( 4 , 9 ) t vb4 dq, cb and dm read input valid time before dqs rising or falling edges. 0.35 ns ( 6 ) t va4 dq, cb and dm read input valid time after dqs rising or falling edges. 0.35 ns ( 6 ) t vb5 cs[1:0]# control valid before m_ck rising edge. 2.62 ns ( 4 ) t va5 cs[1:0]# control valid after m_ck rising edge. 2.62 ns ( 4 ) t vb6 dqs write preamble duration. 4.50 (nominal) ns ( 7 ) t va6 dqs write postamble duration. 3.00 (nominal) ns ( 7 ) notes: 1. see figure 7, ?output timing measurement waveforms? on page 69 . 2. see figure 8, ?input timing measurement waveforms? on page 70 . 3. clock to output valid times are specified with a 0 pf loading. 4. see figure 11, ?ddr sdram write timings? on page 71 . 5. see figure 13 ?dqs falling edge output access time to m_ck rising edge. 6. see figure 12, ?ddr sdram read timings? on page 71 . data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the dqs delay programmed for a 90 degree phase shift. 7. see figure 13, ?write preamble/postamble durations? on page 72 . 8. see figure 15, ?ac test load for ddr sdram signals? on page 73 . 9. address/command pin group; ras# , cas# , we# , ma[12:0] , ba[1:0] . 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 62 order number: 305433, revision: 002 table 29. ddr-ii sdram signal timings symbol parameter min. max. units notes t vb1 dq, cb and dm write output valid time before dqs crossing. 2.12 ns 4 t va1 dq, cb and dm write output valid time after dqs crossing. 2.12 ns 4 t vb3 address and command write output valid before m_ck rising edge 2.12 ns 4 t va3 address and command write output valid after m_ck rising edge 2.12 ns 4 , 8 t vb4 dq, cb and dm read input valid time before dqs rising or falling edges 0.35 ns 6 t va4 dq, cb and dm read input valid time after dqs rising or falling edges 0.35 ns 6 t vb5 cs[1:0]# control valid before m_ck rising edge. 2.12 ns 4 t va5 cs[1:0]# control valid after m_ck rising edge. 2.12 ns 4 t vb6 dqs write preamble duration. 3.75 (nom.) ns 9 t va6 dqs write postamble duration. 2.50 (nom.) ns 9 notes: 1. see figure 7, ?output timing measurement waveforms? on page 69 . 2. see figure 8, ?input timing measurement waveforms? on page 70 . 3. clock to output valid times are specified with a 0 pf loading. 4. see figure 11, ?ddr sdram write timings? on page 71 . 5. see figure 13 ?dqs falling edge output access time to m_ck rising edge. 6. see figure 12, ?ddr sdram read timings? on page 71 . data to strobe read setup and data from strobe read hold minimum requirements specified ar e determined with the dqs delay programmed for a 90 degree phase shift. 7. see figure 15, ?ac test load for ddr sdram signals? on page 73 . 8. address/command pin group: ras#, cas#, we#, ma[12:0], ba[1:0], odt[1:0] . 9. see figure 13, ?write preamble/postamble durations? on page 72 . 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 63 4.4.3 peripheral bus interface signal timings table 30. peripheral bus signal timings symbol parameter min. max. units notes t ov1 output valid delay from m_ck 1 5 ns ( 1 , 3 ) t of output float delay from m_ck 1 5 ns ( 1 , 3 ) t is1 input setup to m_ck 4.5 ns ( 2 ) t ih1 input hold from m_ck 2 ns ( 2 ) t ah1 ale high time 15 ns t av1 ale high to address valid 0 ns t ah2 ale low to address invalid 15 ns t as1 address valid to ale low 15 ns t ao1 ale low to poe# low 0 ns t aw1 ale low to pwe# low 15 ns t ah3 pwe# high to data invalid 15 ns t as2 data valid to pwe# high 60 ns t ac1 ale low to pce[1:0]# low 15 ns notes: 1. see figure 7, ?output timing measurement waveforms? on page 69 . 2. see figure 8, ?input timing measurement waveforms? on page 70 . 3. see figure 14, ?ac test load for all signals except pci and ddr sdram? on page 73 . 4. see table 32, ac measurement conditions. 5. all timing referenced to m_ck is for functional testing, for the cases where m_ck n = ibclk. 6. pbi clock is internal only; 66 mhz with 333 mhz internal bus. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 64 order number: 305433, revision: 002 table 31. pci signal timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max. min. max. min. max. min. max. t ov1 clock to output valid delay for bused signals 0.7 3.8 0.7 3.8 1 6 2 11 ns ( 1 , 2 , 3 ) t ov2 clock to output valid delay for point to point signals 0.7 3.8 0.7 3.8 2 6 2 12 ns ( 1 , 2 , 3 ) t of clock to output float delay 7 7 14 28 ns ( 1 , 7 ) t is1 input setup to clock for bused signals 1.2 1.7 3 7 ns ( 3 , 4 , 8 ) t is2 input setup to clock for point to point signals 1.2 1.7 5 10, 12 ns ( 3 , 4 ) t ih1 input hold time from clock 0.5 0.5 0 0 ns ( 4 ) t rst reset active time 1 1 1 1 ms t rf reset active to output float delay 40 40 40 40 ns ( 5 , 6 ) t is3 req64# to reset setup time 10 10 10 10 clocks t ih2 reset to req64# hold time 0 50 0 50 0 50 0 50 ns t is4 pci-x initialization pattern to reset setup time 10 10 clocks t ih3 reset to pci-x initialization pattern hold time 0500 50 ns notes: 1. see the timing measurement conditions in; figure 7, ?output timing measurement waveforms? on page 69 . 2. see figure 16, ?pci/pci-x tov(max) rising edge ac test load? on page 73 , figure 17, ?pci/pci-x tov(max) falling edge ac test load? on page 74 , and figure 18, ?pci/pci-x tov(min) ac test load? on page 74 . 3. setup time for point-to-point signals applies to req# and gnt # only. all other signals are bused. 4. see the timing measurement conditions in figure 8, ?input timing measurement waveforms? on page 70 . 5. rst# is asserted and deasserted asynchronously with respect to clk. 6. all output drivers must be floated when rst# is active. 7. for purposes of active/float timing measurements, the hi-z or ?off? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. setup time applies only when the device is not dr iving the pin. devices cannot drive and receive signals at the same time. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 65 4.4.4 i 2 c/smbus interface signal timings 4.4.5 uart interface signal timings table 32. i 2 c/smbus signal timings symbol parameter std. mode fast mode units notes min. max min. max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s ( 1 ) t hdsta hold time (repeated) start condition 4 0.6 s ( 1 , 3 ) t low scl clock low time 4.7 1.3 s ( 1 , 2 ) t high scl clock high time 4 0.6 s ( 1 , 2 ) t susta setup time for a repeated start condition 4.7 0.6 s ( 1 ) t hddat data hold time 0 3.45 0 0.9 s ( 1 ) t sudat data setup time 250 100 ns ( 1 ) t sr scl and sda rise time 1000 20 + 0.1 c b 300 ns ( 1 , 4 ) t sf scl and sda fall time 300 20 + 0.1 c b 300 ns ( 1 , 4 ) t susto setup time for stop condition 4 0.6 s ( 1 ) notes: 1. see figure 9, ?i2c/smbus interface signal timings? on page 70 . 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf. 5. std. mode i 2 c signal timings apply for smbus timing. table 33. uart signal timings symbol parameter std. mode units notes min. max t xd1 ux_txd output delay from m_ck rising edge 60 ns 1 t rxs1 ux_rxd data setup time (to m_ck rising edge). 50 ns 2 t rxh1 ux_rxd data hold time (to m_ck rising edge). 50 ns 2 t cts1 ux_cts setup time (to m_ck rising edge). 60 ns t cth1 ux_cts hold time (to m_ck rising edge). 60 ns t rts1 ux_rts setup time (to m_ck rising edge). 60 ns t rth1 ux_rts hold time (to m_ck rising edge). 60 ns notes: 1. see figure 10, ?uart transmitter receiver timing? on page 70 . 2. all timings referenced to m_ck for functional testing, is for cases where m_ck n = ibclk. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 66 order number: 305433, revision: 002 4.4.6 pci express* differential transmitter (tx) output specifications table 34. pci express* tx output specifications symbol parameter min. nom. max. units notes ui unit interval 400 ps 1 v diffp-p differential output voltage .800 1.200 v 2 t rise , t fall driver rise/fall time 0.2 0.4 ui 3 v tx-cm-ac ac common mode 20 mv 4 v tx-cm-dc delta common mode active to sleep mode delta -50 +50 mv rl-diff tx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z tx-out-dc dc differential output impedance 90 100 110 ? 6 z tx-match-dc d+/d- impedance matching -5 +5 % 7 l skew-tx lane to lane skew at tx 500 ps 8 j total total output jitter. 0.35 ui 9 t deye minimum transmitter eye opening. 0.65 ui 10 i tx-short short circuit current -100 100 ma 11 v tx-idle sleep mode voltage output 0 0 20 mv 12 notes: 1. 300 ppm. ui does not account for ssc dictated variations. no test load is necessarily associated with this value. this ui spec is a ?before transmi ssion? specification and represents the nominal time of each bit transmission or width. 2. peak-peak differential voltage. v diffp-p = 2 v dmax . specified at the package pins into a 100 ? test load as shown in figure 19, ?transmitter test load (100 w differential load)? on page 74 . max level set by maximum single ended voltage after a reflection from an open. this value is for the first bit after a transition on the data lines. subsequent bits of the same polarity shall have an amplitude of 6 db (0.5 db) less as measured differentially peak to peak than the specified value. 3. 20?80% at transmitter. slower rise/fall times are better. 4. peak common mode value. | v d+ + v d- |/2 - v cm-dc(avg). 5. 50 mhz to 1.6 ghz. the driver output impedance shall re sult in a differential return loss greater than or equal to 15 db and a common mode return lo ss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance r equirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e., as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* in terconnect differential char acteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. all devices shall employ on-chip adaptive impedance matching circuits to ensure the best possibl e termination/zout for its transmitters (as well as receivers). 7. dc impedance matching between two lanes of a port. 8. between any two lanes within a single transmitter. 9. clock source ppm mismatch is in addition to this value. measured over 250 ui. 10. see figure 20, ?transmitter eye diagram? on page 75 . 11. between any voltage from max supply to gnd with power on or off. 12. squelch condition. both signals brought to v cm-dc- | vd+ - vd- |. 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 67 4.4.7 pci express* differential receiver (rx) input specifications table 35. pci express* rx input specifications symbol parameter min. nom. max. units notes v diffp-p differential input voltage 0.175 1.200 v 1 j total total output jitter. 0.65 ui 2 v cm-ac ac common mode 100 mv 3 t reye receiver eye opening. 0.35 ui 4 rl-diff rx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z rx-out-dc dc differential output impedance 90 100 110 ? 6 z rx-match-dc d+/d- impedance matching -5 +5 % 7 v rx-squelch squelch detect threshold 75 175 mv 8 cin rx ac coupled 400 pf 9 l skew-rx lane to lane skew at rx 20 ui 10 notes: 1. peak-peak differential voltage. v diffp-p = 2 v rmax . measured at the package pins of the receiver. see figure 20, ?transmitter eye diagram? on page 75 . 2. max jitter tolerated by rx. this is the nominal value tolerated at the package pin of the receiver device. a receiver must therefore tolerate any additional jitter generated by the package to the die. 3. peak common mode value. | v d+ + v d- |/2 - v cm-dc(avg) . 4. see figure 21, ?receiver eye opening (differential)? on page 75 . 5. 50 mhz to 1.6 ghz. the driver output impedance shall re sult in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? s for common mode (i.e., as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* in terconnect differential characteristic impedance of 100 ? . applicable during active ( l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. 7. dc impedance matching between two lanes of a port. 8. peak to peak value. measured at the pin of the receiver. differential signal below this level will indicate a squelch condition. 9. all receivers shall be ac coupled to the media. 10. lane skew at the receiver that must be tolerated. 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 68 order number: 305433, revision: 002 4.4.8 boundary scan test signal timings table 36. boundary scan test signal timings symbol parameter min. max units notes t bsf tck frequency 0 0.5t f mhz t bsch tck high time 15 ns measured at 1.5 v ( 1 ). t bscl tck low time 15 ns measured at 1.5 v ( 1 ). t bscr tck rise time 5 ns 0.8 v to 2.0 v ( 1 ) t bscf tck fall time 5 ns 2.0 v to 0.8 v ( 1 ) t bsis1 input setup to tck ? tdi , tms 3ns( 4 ) t bsih1 input hold from tck ? tdi , tms 5ns( 4 ) t bsov1 tdo valid delay 5 15 ns relative to falling edge of tck ( 2 , 3 ). t of1 tdo float delay 5 15 ns relative to falling edge of tck ( 2 , 5 ). notes: 1. not tested. 2. outputs precharged to v cc5 . 3. see figure 7, ?output timing measurement waveforms? on page 69 . 4. see figure 8, ?input timing measurement waveforms? on page 70 . 5. a float condition occurs when the output current becomes less than ilo. float delay is not tested. see figure 7, ?output timing measurement waveforms? on page 69 . 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 69 4.5 ac timing waveforms figure 6. clock timing measurement waveforms figure 7. output timing measurement waveforms t cf t cr t ch t cl t c v tch v ih(min) v il(max) v test v tcl v test clk output float v trise output delay rise output delay fall v tfall t ov t ov t of v tl v th 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 70 order number: 305433, revision: 002 figure 8. input timing measurement waveforms figure 9. i 2 c/smbus interface signal timings figure 10. uart transmitter receiver timing clk input valid v test v test v test t is t ih v tl v th v th v tl v max sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start m_ck ux_txd t xd1 ux_rxd t rxh1 t rxs1 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 71 figure 11. ddr sdram write timings figure 12. ddr sdram read timings m_ck dqs dq t va1 t vb1 t vb5 t va5 cs[1:0]# t vb3 t va3 addr/ctrl dqs# dqs dq t vb4 t va4 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 72 order number: 305433, revision: 002 figure 13. write preamble/postamble durations dqs t vb6 dqs t va6 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 73 4.6 ac test conditions table 37. ac measurement conditions symbol pci-x pci ddr / ddr-ii ddr-ii pbi units v th 0.6 v cc33 0.6 v cc33 2.0 / 1.15 1.15 2.0 v v tl 0.25 v cc33 0.2 v cc33 0.5 / 0.2 0.2 0.8 v v test 0.4 v cc33 0.4 v cc33 1.25 / 0.90 0.90 1.5 v v trise 0.285 v cc33 0.285 v cc33 1.25 / 0.90 0.90 1.5 v v tfall 0.615 v cc33 0.615 v cc33 1.25 / 0.90 0.90 1.5 v v max 0.4 v cc33 0.4 v cc33 1.5 / 0.97 0.97 1.2 v slew rate 1 1.5 1.5 1.0 1.0 1.0 v/ns notes: 1. input signal slew rate is measured between v il and v ih . figure 14. ac test load for all signals except pci and ddr sdram figure 15. ac test load for ddr sdram signals figure 16. pci/pci-x t ov(max) rising edge ac test load output 50pf te s t point 25 ? 30pf 25 ? 1.25v output te st point output te s t point 10pf 25 ? 80333 may 2005 intel ? 80333 i/o processor datasheet datasheet 74 order number: 305433, revision: 002 figure 17. pci/pci-x t ov(max) falling edge ac test load figure 18. pci/pci-x t ov(min) ac test load figure 19. transmitter test load (100 ? differential load) output 10pf 25 ? v cc33 te st point output te st point 10pf 1k ? 1k ? v cc33 d+ d- + - v cm-dc 50 ohm 50 ohm 80333 datasheet intel ? 80333 i/o processor datasheet may 2005 order number: 305433, revision: 002 75 figure 20. transmitter eye diagram figure 21. receiver eye opening (differential) note: transmitter v diffp-p = 2 v dmax ui v dmax v dmin t deye note: transmitter v diffp-p = 2 v rmax ui v rmax v rmin t reye |
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